1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
7 * Author: Markus Niebel <markus.niebel@tq-group.com>
8 *
9 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
10 */
11
12 #include <init.h>
13 #include <net.h>
14 #include <asm/io.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/arch/imx-regs.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/sys_proto.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
22 #include <asm/gpio.h>
23 #include <asm/mach-imx/boot_mode.h>
24 #include <asm/mach-imx/mxc_i2c.h>
25
26 #include <common.h>
27 #include <fsl_esdhc_imx.h>
28 #include <linux/libfdt.h>
29 #include <malloc.h>
30 #include <i2c.h>
31 #include <miiphy.h>
32 #include <mmc.h>
33 #include <netdev.h>
34
35 #include "tqma6_bb.h"
36
37 /* UART */
38 #define UART4_PAD_CTRL ( \
39 PAD_CTL_HYS | \
40 PAD_CTL_PUS_100K_UP | \
41 PAD_CTL_PUE | \
42 PAD_CTL_PKE | \
43 PAD_CTL_SPEED_MED | \
44 PAD_CTL_DSE_40ohm | \
45 PAD_CTL_SRE_SLOW \
46 )
47
48 static iomux_v3_cfg_t const uart4_pads[] = {
49 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B, UART4_PAD_CTRL),
50 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B, UART4_PAD_CTRL),
51 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA, UART4_PAD_CTRL),
52 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA, UART4_PAD_CTRL),
53 };
54
setup_iomuxc_uart4(void)55 static void setup_iomuxc_uart4(void)
56 {
57 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
58 }
59
60 /* MMC */
61 #define USDHC2_PAD_CTRL ( \
62 PAD_CTL_HYS | \
63 PAD_CTL_PUS_47K_UP | \
64 PAD_CTL_SPEED_LOW | \
65 PAD_CTL_DSE_80ohm | \
66 PAD_CTL_SRE_FAST \
67 )
68
69 #define USDHC2_CLK_PAD_CTRL ( \
70 PAD_CTL_HYS | \
71 PAD_CTL_PUS_47K_UP | \
72 PAD_CTL_SPEED_LOW | \
73 PAD_CTL_DSE_40ohm | \
74 PAD_CTL_SRE_FAST \
75 )
76
77 static iomux_v3_cfg_t const usdhc2_pads[] = {
78 NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC2_CLK_PAD_CTRL),
79 NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL),
80 NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL),
81 NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL),
82 NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL),
83 NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL),
84
85 NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, USDHC2_PAD_CTRL), /* CD */
86 NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP, USDHC2_PAD_CTRL), /* WP */
87 };
88
89 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
90 #define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
91
92 static struct fsl_esdhc_cfg usdhc2_cfg = {
93 .esdhc_base = USDHC2_BASE_ADDR,
94 .max_bus_width = 4,
95 };
96
tqma6_bb_board_mmc_getcd(struct mmc * mmc)97 int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
98 {
99 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
100 int ret = 0;
101
102 if (cfg->esdhc_base == USDHC2_BASE_ADDR)
103 ret = !gpio_get_value(USDHC2_CD_GPIO);
104
105 return ret;
106 }
107
tqma6_bb_board_mmc_getwp(struct mmc * mmc)108 int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
109 {
110 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
111 int ret = 0;
112
113 if (cfg->esdhc_base == USDHC2_BASE_ADDR)
114 ret = gpio_get_value(USDHC2_WP_GPIO);
115
116 return ret;
117 }
118
tqma6_bb_board_mmc_init(struct bd_info * bis)119 int tqma6_bb_board_mmc_init(struct bd_info *bis)
120 {
121 int ret;
122
123 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
124
125 ret = gpio_request(USDHC2_CD_GPIO, "mmc-cd");
126 if (!ret)
127 gpio_direction_input(USDHC2_CD_GPIO);
128 ret = gpio_request(USDHC2_WP_GPIO, "mmc-wp");
129 if (!ret)
130 gpio_direction_input(USDHC2_WP_GPIO);
131
132 usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
133 if(fsl_esdhc_initialize(bis, &usdhc2_cfg))
134 puts("WARNING: failed to initialize SD\n");
135
136 return 0;
137 }
138
139 /* Ethernet */
140 #define ENET_PAD_CTRL ( \
141 PAD_CTL_HYS | \
142 PAD_CTL_PUS_100K_UP | \
143 PAD_CTL_PUE | \
144 PAD_CTL_PKE | \
145 PAD_CTL_SPEED_MED | \
146 PAD_CTL_DSE_40ohm | \
147 PAD_CTL_SRE_SLOW \
148 )
149
150 static iomux_v3_cfg_t const enet_pads[] = {
151 NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
152 NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
153 NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL),
154 NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0, ENET_PAD_CTRL),
155 NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1, ENET_PAD_CTRL),
156 NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN, ENET_PAD_CTRL),
157 NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER, ENET_PAD_CTRL),
158 NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0, ENET_PAD_CTRL),
159 NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1, ENET_PAD_CTRL),
160 NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN, ENET_PAD_CTRL),
161 NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER, ENET_PAD_CTRL),
162
163 /* ENET1 reset */
164 NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, ENET_PAD_CTRL),
165 /* ENET1 interrupt */
166 NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09, ENET_PAD_CTRL),
167 };
168
169 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8)
170
setup_iomuxc_enet(void)171 static void setup_iomuxc_enet(void)
172 {
173 int ret;
174
175 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
176
177 /* Reset LAN8720 PHY */
178 ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
179 if (!ret)
180 gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
181 udelay(25000);
182 gpio_set_value(ENET_PHY_RESET_GPIO, 1);
183 }
184
board_eth_init(struct bd_info * bis)185 int board_eth_init(struct bd_info *bis)
186 {
187 return cpu_eth_init(bis);
188 }
189
190 /* GPIO */
191 #define GPIO_PAD_CTRL ( \
192 PAD_CTL_HYS | \
193 PAD_CTL_PUS_100K_UP | \
194 PAD_CTL_PUE | \
195 PAD_CTL_SPEED_MED | \
196 PAD_CTL_DSE_40ohm | \
197 PAD_CTL_SRE_SLOW \
198 )
199
200 #define GPIO_OD_PAD_CTRL ( \
201 PAD_CTL_HYS | \
202 PAD_CTL_PUS_100K_UP | \
203 PAD_CTL_PUE | \
204 PAD_CTL_ODE | \
205 PAD_CTL_SPEED_MED | \
206 PAD_CTL_DSE_40ohm | \
207 PAD_CTL_SRE_SLOW \
208 )
209
210 static iomux_v3_cfg_t const gpio_pads[] = {
211 /* USB_H_PWR */
212 NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00, GPIO_PAD_CTRL),
213 /* USB_OTG_PWR */
214 NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL),
215 /* PCIE_RST */
216 NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07, GPIO_OD_PAD_CTRL),
217 /* UART1_PWRON */
218 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08, GPIO_PAD_CTRL),
219 /* UART2_PWRON */
220 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10, GPIO_PAD_CTRL),
221 /* UART3_PWRON */
222 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12, GPIO_PAD_CTRL),
223 };
224
225 #define GPIO_USB_H_PWR IMX_GPIO_NR(1, 0)
226 #define GPIO_USB_OTG_PWR IMX_GPIO_NR(3, 22)
227 #define GPIO_PCIE_RST IMX_GPIO_NR(6, 7)
228 #define GPIO_UART1_PWRON IMX_GPIO_NR(5, 8)
229 #define GPIO_UART2_PWRON IMX_GPIO_NR(5, 10)
230 #define GPIO_UART3_PWRON IMX_GPIO_NR(5, 12)
231
gpio_init(void)232 static void gpio_init(void)
233 {
234 int ret;
235
236 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
237
238 ret = gpio_request(GPIO_USB_H_PWR, "usb-h-pwr");
239 if (!ret)
240 gpio_direction_output(GPIO_USB_H_PWR, 1);
241 ret = gpio_request(GPIO_USB_OTG_PWR, "usb-otg-pwr");
242 if (!ret)
243 gpio_direction_output(GPIO_USB_OTG_PWR, 1);
244 ret = gpio_request(GPIO_PCIE_RST, "pcie-reset");
245 if (!ret)
246 gpio_direction_output(GPIO_PCIE_RST, 1);
247 ret = gpio_request(GPIO_UART1_PWRON, "uart1-pwr");
248 if (!ret)
249 gpio_direction_output(GPIO_UART1_PWRON, 0);
250 ret = gpio_request(GPIO_UART2_PWRON, "uart2-pwr");
251 if (!ret)
252 gpio_direction_output(GPIO_UART2_PWRON, 0);
253 ret = gpio_request(GPIO_UART3_PWRON, "uart3-pwr");
254 if (!ret)
255 gpio_direction_output(GPIO_UART3_PWRON, 0);
256 }
257
tqma6_iomuxc_spi(void)258 void tqma6_iomuxc_spi(void)
259 {
260 /* No SPI on this baseboard */
261 }
262
tqma6_bb_board_early_init_f(void)263 int tqma6_bb_board_early_init_f(void)
264 {
265 setup_iomuxc_uart4();
266
267 return 0;
268 }
269
tqma6_bb_board_init(void)270 int tqma6_bb_board_init(void)
271 {
272 setup_iomuxc_enet();
273
274 gpio_init();
275
276 /* Turn the UART-couplers on one-after-another */
277 gpio_set_value(GPIO_UART1_PWRON, 1);
278 mdelay(10);
279 gpio_set_value(GPIO_UART2_PWRON, 1);
280 mdelay(10);
281 gpio_set_value(GPIO_UART3_PWRON, 1);
282
283 return 0;
284 }
285
tqma6_bb_board_late_init(void)286 int tqma6_bb_board_late_init(void)
287 {
288 return 0;
289 }
290
tqma6_bb_get_boardname(void)291 const char *tqma6_bb_get_boardname(void)
292 {
293 return "WRU-IV";
294 }
295
296 static const struct boot_mode board_boot_modes[] = {
297 /* 4 bit bus width */
298 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
299 /* 8 bit bus width */
300 {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
301 { NULL, 0 },
302 };
303
misc_init_r(void)304 int misc_init_r(void)
305 {
306 add_board_boot_modes(board_boot_modes);
307
308 return 0;
309 }
310
311 #define WRU4_USB_H1_PWR IMX_GPIO_NR(1, 0)
312 #define WRU4_USB_OTG_PWR IMX_GPIO_NR(3, 22)
313
board_ehci_hcd_init(int port)314 int board_ehci_hcd_init(int port)
315 {
316 int ret;
317
318 ret = gpio_request(WRU4_USB_H1_PWR, "usb-h1-pwr");
319 if (!ret)
320 gpio_direction_output(WRU4_USB_H1_PWR, 1);
321
322 ret = gpio_request(WRU4_USB_OTG_PWR, "usb-OTG-pwr");
323 if (!ret)
324 gpio_direction_output(WRU4_USB_OTG_PWR, 1);
325
326 return 0;
327 }
328
board_ehci_power(int port,int on)329 int board_ehci_power(int port, int on)
330 {
331 if (port)
332 gpio_set_value(WRU4_USB_OTG_PWR, on);
333 else
334 gpio_set_value(WRU4_USB_H1_PWR, on);
335
336 return 0;
337 }
338
339 /*
340 * Device Tree Support
341 */
342 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
tqma6_bb_ft_board_setup(void * blob,struct bd_info * bd)343 void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd)
344 {
345 /* TBD */
346 }
347 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
348