1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8 #include <init.h>
9 #include <net.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <env.h>
14 #include <malloc.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/global_data.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <asm/gpio.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/sata.h>
22 #include <mmc.h>
23 #include <fsl_esdhc_imx.h>
24 #include <asm/arch/crm_regs.h>
25 #include <asm/io.h>
26 #include <asm/arch/sys_proto.h>
27 #include <micrel.h>
28 #include <miiphy.h>
29 #include <netdev.h>
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
34 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
35 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36
37 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
39
40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
41 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43
44 #define WDT_EN IMX_GPIO_NR(5, 4)
45 #define WDT_TRG IMX_GPIO_NR(3, 19)
46
dram_init(void)47 int dram_init(void)
48 {
49 gd->ram_size = imx_ddr_size();
50
51 return 0;
52 }
53
54 static iomux_v3_cfg_t const uart2_pads[] = {
55 IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
56 IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
57 };
58
59 static iomux_v3_cfg_t const usdhc3_pads[] = {
60 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
62 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
63 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
64 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
65 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
66 };
67
68 static iomux_v3_cfg_t const wdog_pads[] = {
69 IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
70 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
71 };
72
mx6_rgmii_rework(struct phy_device * phydev)73 int mx6_rgmii_rework(struct phy_device *phydev)
74 {
75 /*
76 * Bug: Apparently uDoo does not works with Gigabit switches...
77 * Limiting speed to 10/100Mbps, and setting master mode, seems to
78 * be the only way to have a successfull PHY auto negotiation.
79 * How to fix: Understand why Linux kernel do not have this issue.
80 */
81 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
82
83 /* control data pad skew - devaddr = 0x02, register = 0x04 */
84 ksz9031_phy_extended_write(phydev, 0x02,
85 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
86 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
87 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
88 ksz9031_phy_extended_write(phydev, 0x02,
89 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
90 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
91 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
92 ksz9031_phy_extended_write(phydev, 0x02,
93 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
94 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
95 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
96 ksz9031_phy_extended_write(phydev, 0x02,
97 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
98 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
99 return 0;
100 }
101
102 static iomux_v3_cfg_t const enet_pads1[] = {
103 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
104 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
105 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
106 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
107 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
108 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
109 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
110 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
111 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
112 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
113 /* RGMII reset */
114 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
115 /* Ethernet power supply */
116 IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
117 /* pin 32 - 1 - (MODE0) all */
118 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
119 /* pin 31 - 1 - (MODE1) all */
120 IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
121 /* pin 28 - 1 - (MODE2) all */
122 IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
123 /* pin 27 - 1 - (MODE3) all */
124 IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
125 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
126 IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
127 };
128
129 static iomux_v3_cfg_t const enet_pads2[] = {
130 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
131 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
132 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
133 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
134 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
135 };
136
setup_iomux_enet(void)137 static void setup_iomux_enet(void)
138 {
139 SETUP_IOMUX_PADS(enet_pads1);
140 udelay(20);
141 gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
142
143 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
144
145 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
146 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
147 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
148 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
149 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
150 udelay(1000);
151
152 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
153
154 /* Need 100ms delay to exit from reset. */
155 udelay(1000 * 100);
156
157 gpio_free(IMX_GPIO_NR(6, 24));
158 gpio_free(IMX_GPIO_NR(6, 25));
159 gpio_free(IMX_GPIO_NR(6, 27));
160 gpio_free(IMX_GPIO_NR(6, 28));
161 gpio_free(IMX_GPIO_NR(6, 29));
162
163 SETUP_IOMUX_PADS(enet_pads2);
164 }
165
setup_iomux_uart(void)166 static void setup_iomux_uart(void)
167 {
168 SETUP_IOMUX_PADS(uart2_pads);
169 }
170
setup_iomux_wdog(void)171 static void setup_iomux_wdog(void)
172 {
173 SETUP_IOMUX_PADS(wdog_pads);
174 gpio_direction_output(WDT_TRG, 0);
175 gpio_direction_output(WDT_EN, 1);
176 gpio_direction_input(WDT_TRG);
177 }
178
179 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
180
board_mmc_getcd(struct mmc * mmc)181 int board_mmc_getcd(struct mmc *mmc)
182 {
183 return 1; /* Always present */
184 }
185
board_eth_init(struct bd_info * bis)186 int board_eth_init(struct bd_info *bis)
187 {
188 uint32_t base = IMX_FEC_BASE;
189 struct mii_dev *bus = NULL;
190 struct phy_device *phydev = NULL;
191 int ret;
192
193 setup_iomux_enet();
194
195 #ifdef CONFIG_FEC_MXC
196 bus = fec_get_miibus(base, -1);
197 if (!bus)
198 return -EINVAL;
199 /* scan phy 4,5,6,7 */
200 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
201
202 if (!phydev) {
203 ret = -EINVAL;
204 goto free_bus;
205 }
206 printf("using phy at %d\n", phydev->addr);
207 ret = fec_probe(bis, -1, base, bus, phydev);
208 if (ret)
209 goto free_phydev;
210 #endif
211 return 0;
212
213 free_phydev:
214 free(phydev);
215 free_bus:
216 free(bus);
217 return ret;
218 }
219
board_mmc_init(struct bd_info * bis)220 int board_mmc_init(struct bd_info *bis)
221 {
222 SETUP_IOMUX_PADS(usdhc3_pads);
223 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
224 usdhc_cfg.max_bus_width = 4;
225
226 return fsl_esdhc_initialize(bis, &usdhc_cfg);
227 }
228
board_early_init_f(void)229 int board_early_init_f(void)
230 {
231 setup_iomux_wdog();
232 setup_iomux_uart();
233
234 return 0;
235 }
236
board_phy_config(struct phy_device * phydev)237 int board_phy_config(struct phy_device *phydev)
238 {
239 mx6_rgmii_rework(phydev);
240 if (phydev->drv->config)
241 phydev->drv->config(phydev);
242
243 return 0;
244 }
245
board_init(void)246 int board_init(void)
247 {
248 /* address of boot parameters */
249 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
250
251 #ifdef CONFIG_SATA
252 setup_sata();
253 #endif
254 return 0;
255 }
256
board_late_init(void)257 int board_late_init(void)
258 {
259 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
260 if (is_cpu_type(MXC_CPU_MX6Q))
261 env_set("board_rev", "MX6Q");
262 else
263 env_set("board_rev", "MX6DL");
264 #endif
265 return 0;
266 }
267
checkboard(void)268 int checkboard(void)
269 {
270 if (is_cpu_type(MXC_CPU_MX6Q))
271 puts("Board: Udoo Quad\n");
272 else
273 puts("Board: Udoo DualLite\n");
274
275 return 0;
276 }
277