1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015-2019 Variscite Ltd.
4 * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
5 * Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
6 */
7
8 #include <init.h>
9 #include <net.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/global_data.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/mxc_i2c.h>
17 #include <dm.h>
18 #include <fsl_esdhc_imx.h>
19 #include <i2c_eeprom.h>
20 #include <linux/bitops.h>
21 #include <malloc.h>
22 #include <miiphy.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
dram_init(void)26 int dram_init(void)
27 {
28 gd->ram_size = imx_ddr_size();
29
30 return 0;
31 }
32
33 #ifdef CONFIG_NAND_MXS
34 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
35 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
36 PAD_CTL_SRE_FAST)
37 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
38 static iomux_v3_cfg_t const nand_pads[] = {
39 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
40 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
41 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
42 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
43 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
44 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
45 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
46 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
47 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
48 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
49 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
50 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
51 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
52 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
53 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
54 MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
55 };
56
setup_gpmi_nand(void)57 static void setup_gpmi_nand(void)
58 {
59 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
60
61 /* config gpmi nand iomux */
62 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
63
64 clrbits_le32(&mxc_ccm->CCGR4,
65 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
66 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
67 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
68 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
69 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
70
71 /*
72 * config gpmi and bch clock to 100 MHz
73 * bch/gpmi select PLL2 PFD2 400M
74 * 100M = 400M / 4
75 */
76 clrbits_le32(&mxc_ccm->cscmr1,
77 MXC_CCM_CSCMR1_BCH_CLK_SEL |
78 MXC_CCM_CSCMR1_GPMI_CLK_SEL);
79 clrsetbits_le32(&mxc_ccm->cscdr1,
80 MXC_CCM_CSCDR1_BCH_PODF_MASK |
81 MXC_CCM_CSCDR1_GPMI_PODF_MASK,
82 (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
83 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
84
85 /* enable gpmi and bch clock gating */
86 setbits_le32(&mxc_ccm->CCGR4,
87 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
88 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
89 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
90 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
91 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
92
93 /* enable apbh clock gating */
94 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
95 }
96 #endif
97
98 #ifdef CONFIG_FEC_MXC
setup_fec(int fec_id)99 static int setup_fec(int fec_id)
100 {
101 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
102 int ret;
103
104 if (fec_id == 0) {
105 /*
106 * Use 50M anatop loopback REF_CLK1 for ENET1,
107 * clear gpr1[13], set gpr1[17].
108 */
109 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
110 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
111 } else {
112 /*
113 * Use 50M anatop loopback REF_CLK2 for ENET2,
114 * clear gpr1[14], set gpr1[18].
115 */
116 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
117 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
118 }
119
120 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
121 if (ret)
122 return ret;
123
124 enable_enet_clk(1);
125
126 return 0;
127 }
128
board_phy_config(struct phy_device * phydev)129 int board_phy_config(struct phy_device *phydev)
130 {
131 /*
132 * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
133 * 50 MHz RMII clock mode.
134 */
135 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
136
137 if (phydev->drv->config)
138 phydev->drv->config(phydev);
139
140 return 0;
141 }
142 #endif /* CONFIG_FEC_MXC */
143
board_init(void)144 int board_init(void)
145 {
146 /* Address of boot parameters */
147 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
148
149 #ifdef CONFIG_FEC_MXC
150 setup_fec(CONFIG_FEC_ENET_DEV);
151 #endif
152
153 #ifdef CONFIG_NAND_MXS
154 setup_gpmi_nand();
155 #endif
156 return 0;
157 }
158
159 /* length of strings stored in the eeprom */
160 #define DART6UL_PN_LEN 16
161 #define DART6UL_ASSY_LEN 16
162 #define DART6UL_DATE_LEN 12
163
164 /* eeprom content, 512 bytes */
165 struct dart6ul_info {
166 u32 magic;
167 u8 partnumber[DART6UL_PN_LEN];
168 u8 assy[DART6UL_ASSY_LEN];
169 u8 date[DART6UL_DATE_LEN];
170 u32 custom_addr_val[32];
171 struct cmd {
172 u8 addr;
173 u8 index;
174 } custom_cmd[150];
175 u8 res[33];
176 u8 som_info;
177 u8 ddr_size;
178 u8 crc;
179 } __attribute__ ((__packed__));
180
181 #define DART6UL_INFO_STORAGE_GET(n) ((n) & 0x3)
182 #define DART6UL_INFO_WIFI_GET(n) ((n) >> 2 & 0x1)
183 #define DART6UL_INFO_REV_GET(n) ((n) >> 3 & 0x3)
184 #define DART6UL_DDRSIZE(n) ((n) * SZ_128M)
185 #define DART6UL_INFO_MAGIC 0x32524156
186
som_info_storage_to_str(u8 som_info)187 static const char *som_info_storage_to_str(u8 som_info)
188 {
189 switch (DART6UL_INFO_STORAGE_GET(som_info)) {
190 case 0x0: return "none (SD only)";
191 case 0x1: return "NAND";
192 case 0x2: return "eMMC";
193 default: return "unknown";
194 }
195 }
196
som_info_rev_to_str(u8 som_info)197 static const char *som_info_rev_to_str(u8 som_info)
198 {
199 switch (DART6UL_INFO_REV_GET(som_info)) {
200 case 0x0: return "2.4G";
201 case 0x1: return "5G";
202 default: return "unknown";
203 }
204 }
205
checkboard(void)206 int checkboard(void)
207 {
208 const char *path = "eeprom0";
209 struct dart6ul_info *info;
210 struct udevice *dev;
211 int ret, off;
212
213 off = fdt_path_offset(gd->fdt_blob, path);
214 if (off < 0) {
215 printf("%s: fdt_path_offset() failed: %d\n", __func__, off);
216 return off;
217 }
218
219 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
220 if (ret) {
221 printf("%s: uclass_get_device_by_of_offset() failed: %d\n", __func__, ret);
222 return ret;
223 }
224
225 info = malloc(sizeof(struct dart6ul_info));
226 if (!info)
227 return -ENOMEM;
228
229 ret = i2c_eeprom_read(dev, 0, (uint8_t *)info,
230 sizeof(struct dart6ul_info));
231 if (ret) {
232 printf("%s: i2c_eeprom_read() failed: %d\n", __func__, ret);
233 free(info);
234 return ret;
235 }
236
237 if (info->magic != DART6UL_INFO_MAGIC) {
238 printf("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n",
239 info->magic, DART6UL_INFO_MAGIC);
240 /* do not fail if the content is invalid */
241 free(info);
242 return 0;
243 }
244
245 /* make sure strings are null terminated */
246 info->partnumber[DART6UL_PN_LEN - 1] = '\0';
247 info->assy[DART6UL_ASSY_LEN - 1] = '\0';
248 info->date[DART6UL_DATE_LEN - 1] = '\0';
249
250 printf("Board: PN: %s, Assy: %s, Date: %s\n"
251 " Storage: %s, Wifi: %s, DDR: %d MiB, Rev: %s\n",
252 info->partnumber,
253 info->assy,
254 info->date,
255 som_info_storage_to_str(info->som_info),
256 DART6UL_INFO_WIFI_GET(info->som_info) ? "yes" : "no",
257 DART6UL_DDRSIZE(info->ddr_size) / SZ_1M,
258 som_info_rev_to_str(info->som_info));
259
260 free(info);
261
262 return 0;
263 }
264