1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Based on corenet_ds ddr code
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <hwconfig.h>
9 #include <init.h>
10 #include <log.h>
11 #include <asm/global_data.h>
12 #include <asm/mmu.h>
13 #include <fsl_ddr_sdram.h>
14 #include <fsl_ddr_dimm_params.h>
15 #include <asm/fsl_law.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19
20 struct board_specific_parameters {
21 u32 n_ranks;
22 u32 datarate_mhz_high;
23 u32 clk_adjust;
24 u32 wrlvl_start;
25 u32 cpo;
26 u32 write_data_delay;
27 u32 force_2t;
28 };
29
30 /*
31 * This table contains all valid speeds we want to override with board
32 * specific parameters. datarate_mhz_high values need to be in ascending order
33 * for each n_ranks group.
34 */
35 static const struct board_specific_parameters udimm0[] = {
36 /*
37 * memory controller 0
38 * num| hi| clk| wrlvl | cpo |wrdata|2T
39 * ranks| mhz|adjst| start | |delay |
40 */
41 {4, 850, 4, 6, 0xff, 2, 0},
42 {4, 950, 5, 7, 0xff, 2, 0},
43 {4, 1050, 5, 8, 0xff, 2, 0},
44 {4, 1250, 5, 10, 0xff, 2, 0},
45 {4, 1350, 5, 11, 0xff, 2, 0},
46 {4, 1666, 5, 12, 0xff, 2, 0},
47 {2, 850, 5, 6, 0xff, 2, 0},
48 {2, 1050, 5, 7, 0xff, 2, 0},
49 {2, 1250, 4, 6, 0xff, 2, 0},
50 {2, 1350, 5, 7, 0xff, 2, 0},
51 {2, 1666, 5, 8, 0xff, 2, 0},
52 {1, 1250, 4, 6, 0xff, 2, 0},
53 {1, 1335, 4, 7, 0xff, 2, 0},
54 {1, 1666, 4, 8, 0xff, 2, 0},
55 {}
56 };
57
58 /*
59 * The two slots have slightly different timing. The center values are good
60 * for both slots. We use identical speed tables for them. In future use, if
61 * DIMMs have fewer center values that require two separated tables, copy the
62 * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
63 */
64 static const struct board_specific_parameters *udimms[] = {
65 udimm0,
66 udimm0,
67 };
68
69 static const struct board_specific_parameters rdimm0[] = {
70 /*
71 * memory controller 0
72 * num| hi| clk| wrlvl | cpo |wrdata|2T
73 * ranks| mhz|adjst| start | |delay |
74 */
75 {4, 850, 4, 6, 0xff, 2, 0},
76 {4, 950, 5, 7, 0xff, 2, 0},
77 {4, 1050, 5, 8, 0xff, 2, 0},
78 {4, 1250, 5, 10, 0xff, 2, 0},
79 {4, 1350, 5, 11, 0xff, 2, 0},
80 {4, 1666, 5, 12, 0xff, 2, 0},
81 {2, 850, 4, 6, 0xff, 2, 0},
82 {2, 1050, 4, 7, 0xff, 2, 0},
83 {2, 1666, 4, 8, 0xff, 2, 0},
84 {1, 850, 4, 5, 0xff, 2, 0},
85 {1, 950, 4, 7, 0xff, 2, 0},
86 {1, 1666, 4, 8, 0xff, 2, 0},
87 {}
88 };
89
90 /*
91 * The two slots have slightly different timing. See comments above.
92 */
93 static const struct board_specific_parameters *rdimms[] = {
94 rdimm0,
95 rdimm0,
96 };
97
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)98 void fsl_ddr_board_options(memctl_options_t *popts,
99 dimm_params_t *pdimm,
100 unsigned int ctrl_num)
101 {
102 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
103 ulong ddr_freq;
104
105 if (ctrl_num > 1) {
106 printf("Wrong parameter for controller number %d", ctrl_num);
107 return;
108 }
109 if (!pdimm->n_ranks)
110 return;
111
112 if (popts->registered_dimm_en)
113 pbsp = rdimms[ctrl_num];
114 else
115 pbsp = udimms[ctrl_num];
116
117
118 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
119 * freqency and n_banks specified in board_specific_parameters table.
120 */
121 ddr_freq = get_ddr_freq(0) / 1000000;
122 while (pbsp->datarate_mhz_high) {
123 if (pbsp->n_ranks == pdimm->n_ranks) {
124 if (ddr_freq <= pbsp->datarate_mhz_high) {
125 popts->cpo_override = pbsp->cpo;
126 popts->write_data_delay =
127 pbsp->write_data_delay;
128 popts->clk_adjust = pbsp->clk_adjust;
129 popts->wrlvl_start = pbsp->wrlvl_start;
130 popts->twot_en = pbsp->force_2t;
131 goto found;
132 }
133 pbsp_highest = pbsp;
134 }
135 pbsp++;
136 }
137
138 if (pbsp_highest) {
139 printf("Error: board specific timing not found for data rate %lu MT/s!\nTrying to use the highest speed (%u) parameters\n",
140 ddr_freq, pbsp_highest->datarate_mhz_high);
141 popts->cpo_override = pbsp_highest->cpo;
142 popts->write_data_delay = pbsp_highest->write_data_delay;
143 popts->clk_adjust = pbsp_highest->clk_adjust;
144 popts->wrlvl_start = pbsp_highest->wrlvl_start;
145 popts->twot_en = pbsp_highest->force_2t;
146 } else {
147 panic("DIMM is not supported by this board");
148 }
149 found:
150 /*
151 * Factors to consider for half-strength driver enable:
152 * - number of DIMMs installed
153 */
154 popts->half_strength_driver_enable = 0;
155 /*
156 * Write leveling override
157 */
158 popts->wrlvl_override = 1;
159 popts->wrlvl_sample = 0xf;
160
161 /*
162 * Rtt and Rtt_WR override
163 */
164 popts->rtt_override = 0;
165
166 /* Enable ZQ calibration */
167 popts->zq_en = 1;
168
169 /* DHC_EN =1, ODT = 60 Ohm */
170 popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
171 }
172
dram_init(void)173 int dram_init(void)
174 {
175 phys_size_t dram_size;
176
177 puts("Initializing....");
178
179 if (!fsl_use_spd())
180 panic("Cyrus only supports using SPD for DRAM\n");
181
182 puts("using SPD\n");
183 dram_size = fsl_ddr_sdram();
184
185 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
186 dram_size *= 0x100000;
187
188 debug(" DDR: ");
189 gd->ram_size = dram_size;
190
191 return 0;
192 }
193