1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2014 O.S. Systems Software LTDA.
5 *
6 * Author: Fabio Estevam <fabio.estevam@freescale.com>
7 */
8
9 #include <common.h>
10 #include <image.h>
11 #include <init.h>
12 #include <log.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/mx6-pins.h>
18 #include <asm/arch/mxc_hdmi.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/global_data.h>
21 #include <asm/gpio.h>
22 #include <asm/mach-imx/iomux-v3.h>
23 #include <asm/mach-imx/mxc_i2c.h>
24 #include <asm/mach-imx/boot_mode.h>
25 #include <asm/mach-imx/video.h>
26 #include <asm/mach-imx/sata.h>
27 #include <asm/io.h>
28 #include <env.h>
29 #include <linux/delay.h>
30 #include <linux/sizes.h>
31 #include <common.h>
32 #include <miiphy.h>
33 #include <netdev.h>
34 #include <phy.h>
35 #include <i2c.h>
36 #include <power/pmic.h>
37 #include <power/pfuze100_pmic.h>
38
39 DECLARE_GLOBAL_DATA_PTR;
40
41 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
42 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44
45 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47
48 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
50 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
51
52 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
53 #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
54 #define REV_DETECTION IMX_GPIO_NR(2, 28)
55
56 /* Speed defined in Kconfig is only applicable when not using DM_I2C. */
57 #if CONFIG_IS_ENABLED(DM_I2C)
58 #define I2C1_SPEED_NON_DM 0
59 #define I2C2_SPEED_NON_DM 0
60 #else
61 #define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED
62 #define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED
63 #endif
64
65 static bool with_pmic;
66
dram_init(void)67 int dram_init(void)
68 {
69 gd->ram_size = imx_ddr_size();
70
71 return 0;
72 }
73
74 static iomux_v3_cfg_t const uart1_pads[] = {
75 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
76 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
77 };
78
79 static iomux_v3_cfg_t const enet_pads[] = {
80 /* AR8031 PHY Reset */
81 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
82 };
83
84 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
85 /* AR8035 POWER */
86 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
87 };
88
89 static iomux_v3_cfg_t const rev_detection_pad[] = {
90 IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
91 };
92
setup_iomux_uart(void)93 static void setup_iomux_uart(void)
94 {
95 SETUP_IOMUX_PADS(uart1_pads);
96 }
97
setup_iomux_enet(void)98 static void setup_iomux_enet(void)
99 {
100 SETUP_IOMUX_PADS(enet_pads);
101
102 if (with_pmic) {
103 SETUP_IOMUX_PADS(enet_ar8035_power_pads);
104 /* enable AR8035 POWER */
105 gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
106 gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
107 }
108 /* wait until 3.3V of PHY and clock become stable */
109 mdelay(10);
110
111 /* Reset AR8031 PHY */
112 gpio_request(ETH_PHY_RESET, "PHY_RESET");
113 gpio_direction_output(ETH_PHY_RESET, 0);
114 mdelay(10);
115 gpio_set_value(ETH_PHY_RESET, 1);
116 udelay(100);
117 }
118
ar8031_phy_fixup(struct phy_device * phydev)119 static int ar8031_phy_fixup(struct phy_device *phydev)
120 {
121 unsigned short val;
122 int mask;
123
124 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
125 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
126 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
127 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
128
129 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
130 if (with_pmic)
131 mask = 0xffe7; /* AR8035 */
132 else
133 mask = 0xffe3; /* AR8031 */
134
135 val &= mask;
136 val |= 0x18;
137 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
138
139 /* introduce tx clock delay */
140 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
141 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
142 val |= 0x0100;
143 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
144
145 return 0;
146 }
147
board_phy_config(struct phy_device * phydev)148 int board_phy_config(struct phy_device *phydev)
149 {
150 ar8031_phy_fixup(phydev);
151
152 if (phydev->drv->config)
153 phydev->drv->config(phydev);
154
155 return 0;
156 }
157
158 #if defined(CONFIG_VIDEO_IPUV3)
159 struct i2c_pads_info mx6q_i2c2_pad_info = {
160 .scl = {
161 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
162 | MUX_PAD_CTRL(I2C_PAD_CTRL),
163 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
164 | MUX_PAD_CTRL(I2C_PAD_CTRL),
165 .gp = IMX_GPIO_NR(4, 12)
166 },
167 .sda = {
168 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
169 | MUX_PAD_CTRL(I2C_PAD_CTRL),
170 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
171 | MUX_PAD_CTRL(I2C_PAD_CTRL),
172 .gp = IMX_GPIO_NR(4, 13)
173 }
174 };
175
176 struct i2c_pads_info mx6dl_i2c2_pad_info = {
177 .scl = {
178 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
179 | MUX_PAD_CTRL(I2C_PAD_CTRL),
180 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
181 | MUX_PAD_CTRL(I2C_PAD_CTRL),
182 .gp = IMX_GPIO_NR(4, 12)
183 },
184 .sda = {
185 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
186 | MUX_PAD_CTRL(I2C_PAD_CTRL),
187 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
188 | MUX_PAD_CTRL(I2C_PAD_CTRL),
189 .gp = IMX_GPIO_NR(4, 13)
190 }
191 };
192
193 struct i2c_pads_info mx6q_i2c3_pad_info = {
194 .scl = {
195 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
196 | MUX_PAD_CTRL(I2C_PAD_CTRL),
197 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
198 | MUX_PAD_CTRL(I2C_PAD_CTRL),
199 .gp = IMX_GPIO_NR(1, 5)
200 },
201 .sda = {
202 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
203 | MUX_PAD_CTRL(I2C_PAD_CTRL),
204 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
205 | MUX_PAD_CTRL(I2C_PAD_CTRL),
206 .gp = IMX_GPIO_NR(7, 11)
207 }
208 };
209
210 struct i2c_pads_info mx6dl_i2c3_pad_info = {
211 .scl = {
212 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
213 | MUX_PAD_CTRL(I2C_PAD_CTRL),
214 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
215 | MUX_PAD_CTRL(I2C_PAD_CTRL),
216 .gp = IMX_GPIO_NR(1, 5)
217 },
218 .sda = {
219 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
220 | MUX_PAD_CTRL(I2C_PAD_CTRL),
221 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
222 | MUX_PAD_CTRL(I2C_PAD_CTRL),
223 .gp = IMX_GPIO_NR(7, 11)
224 }
225 };
226
227 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
228 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
229 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
230 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
231 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
232 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
233 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
234 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
235 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
236 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
237 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
238 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
239 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
240 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
241 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
242 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
243 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
244 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
245 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
246 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
247 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
248 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
249 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
250 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
251 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
252 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
253 };
254
do_enable_hdmi(struct display_info_t const * dev)255 static void do_enable_hdmi(struct display_info_t const *dev)
256 {
257 imx_enable_hdmi_phy();
258 }
259
detect_i2c(struct display_info_t const * dev)260 static int detect_i2c(struct display_info_t const *dev)
261 {
262 #if CONFIG_IS_ENABLED(DM_I2C)
263 struct udevice *bus, *udev;
264 int rc;
265
266 rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
267 if (rc)
268 return rc;
269 rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
270 if (rc)
271 return 0;
272 return 1;
273 #else
274 return (0 == i2c_set_bus_num(dev->bus)) &&
275 (0 == i2c_probe(dev->addr));
276 #endif
277 }
278
enable_fwadapt_7wvga(struct display_info_t const * dev)279 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
280 {
281 SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
282
283 gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
284 gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
285 gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
286 gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
287 }
288
289 struct display_info_t const displays[] = {{
290 .bus = -1,
291 .addr = 0,
292 .pixfmt = IPU_PIX_FMT_RGB24,
293 .detect = detect_hdmi,
294 .enable = do_enable_hdmi,
295 .mode = {
296 .name = "HDMI",
297 .refresh = 60,
298 .xres = 1024,
299 .yres = 768,
300 .pixclock = 15385,
301 .left_margin = 220,
302 .right_margin = 40,
303 .upper_margin = 21,
304 .lower_margin = 7,
305 .hsync_len = 60,
306 .vsync_len = 10,
307 .sync = FB_SYNC_EXT,
308 .vmode = FB_VMODE_NONINTERLACED
309 } }, {
310 .bus = 1,
311 .addr = 0x10,
312 .pixfmt = IPU_PIX_FMT_RGB666,
313 .detect = detect_i2c,
314 .enable = enable_fwadapt_7wvga,
315 .mode = {
316 .name = "FWBADAPT-LCD-F07A-0102",
317 .refresh = 60,
318 .xres = 800,
319 .yres = 480,
320 .pixclock = 33260,
321 .left_margin = 128,
322 .right_margin = 128,
323 .upper_margin = 22,
324 .lower_margin = 22,
325 .hsync_len = 1,
326 .vsync_len = 1,
327 .sync = 0,
328 .vmode = FB_VMODE_NONINTERLACED
329 } } };
330 size_t display_count = ARRAY_SIZE(displays);
331
setup_display(void)332 static void setup_display(void)
333 {
334 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
335 int reg;
336
337 enable_ipu_clock();
338 imx_setup_hdmi();
339
340 reg = readl(&mxc_ccm->chsccdr);
341 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
342 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
343 writel(reg, &mxc_ccm->chsccdr);
344
345 /* Disable LCD backlight */
346 SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
347 gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
348 gpio_direction_input(IMX_GPIO_NR(4, 20));
349 }
350 #endif /* CONFIG_VIDEO_IPUV3 */
351
board_early_init_f(void)352 int board_early_init_f(void)
353 {
354 setup_iomux_uart();
355 #ifdef CONFIG_SATA
356 setup_sata();
357 #endif
358
359 return 0;
360 }
361
362 #define PMIC_I2C_BUS 2
363
power_init_board(void)364 int power_init_board(void)
365 {
366 struct udevice *dev;
367 int reg, ret;
368
369 ret = pmic_get("pfuze100@8", &dev);
370 if (ret < 0) {
371 debug("pmic_get() ret %d\n", ret);
372 return 0;
373 }
374
375 reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
376 if (reg < 0) {
377 debug("pmic_reg_read() ret %d\n", reg);
378 return 0;
379 }
380 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
381 with_pmic = true;
382
383 /* Set VGEN2 to 1.5V and enable */
384 reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
385 reg &= ~(LDO_VOL_MASK);
386 reg |= (LDOA_1_50V | (1 << (LDO_EN)));
387 pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
388 return 0;
389 }
390
391 /*
392 * Do not overwrite the console
393 * Use always serial for U-Boot console
394 */
overwrite_console(void)395 int overwrite_console(void)
396 {
397 return 1;
398 }
399
400 #ifdef CONFIG_CMD_BMODE
401 static const struct boot_mode board_boot_modes[] = {
402 /* 4 bit bus width */
403 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
404 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
405 {NULL, 0},
406 };
407 #endif
408
is_revc1(void)409 static bool is_revc1(void)
410 {
411 SETUP_IOMUX_PADS(rev_detection_pad);
412 gpio_request(REV_DETECTION, "REV_DETECT");
413 gpio_direction_input(REV_DETECTION);
414
415 if (gpio_get_value(REV_DETECTION))
416 return true;
417 else
418 return false;
419 }
420
is_revd1(void)421 static bool is_revd1(void)
422 {
423 if (with_pmic)
424 return true;
425 else
426 return false;
427 }
428
board_late_init(void)429 int board_late_init(void)
430 {
431 #ifdef CONFIG_CMD_BMODE
432 add_board_boot_modes(board_boot_modes);
433 #endif
434
435 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
436 if (is_mx6dqp())
437 env_set("board_rev", "MX6QP");
438 else if (is_mx6dq())
439 env_set("board_rev", "MX6Q");
440 else
441 env_set("board_rev", "MX6DL");
442
443 if (is_revd1())
444 env_set("board_name", "D1");
445 else if (is_revc1())
446 env_set("board_name", "C1");
447 else
448 env_set("board_name", "B1");
449 #endif
450 setup_iomux_enet();
451
452 if (is_revd1())
453 puts("Board: Wandboard rev D1\n");
454 else if (is_revc1())
455 puts("Board: Wandboard rev C1\n");
456 else
457 puts("Board: Wandboard rev B1\n");
458
459 return 0;
460 }
461
board_init(void)462 int board_init(void)
463 {
464 /* address of boot parameters */
465 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
466
467 #if defined(CONFIG_VIDEO_IPUV3)
468 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
469 if (is_mx6dq() || is_mx6dqp()) {
470 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
471 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
472 } else {
473 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
474 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
475 }
476
477 setup_display();
478 #endif
479
480 return 0;
481 }
482
483 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)484 int board_fit_config_name_match(const char *name)
485 {
486 if (is_mx6dq()) {
487 if (!strcmp(name, "imx6q-wandboard-revd1"))
488 return 0;
489 } else if (is_mx6dqp()) {
490 if (!strcmp(name, "imx6qp-wandboard-revd1"))
491 return 0;
492 } else if (is_mx6dl() || is_mx6solo()) {
493 if (!strcmp(name, "imx6dl-wandboard-revd1"))
494 return 0;
495 }
496
497 return -EINVAL;
498 }
499 #endif
500