1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2008 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8
9 #include <fsl_ddr_sdram.h>
10 #include <fsl_ddr_dimm_params.h>
11
get_spd(ddr2_spd_eeprom_t * spd,unsigned char i2c_address)12 void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
13 {
14 i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
15
16 /* We use soldered memory, but use an SPD EEPROM to describe it.
17 * The SPD has an unspecified dimm type, but the DDR2 initialization
18 * code requires a specific type to be specified. This sets the type
19 * as a standard unregistered SO-DIMM. */
20 if (spd->dimm_type == 0) {
21 spd->dimm_type = 0x4;
22 ((uchar *)spd)[63] += 0x4;
23 }
24 }
25
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)26 void fsl_ddr_board_options(memctl_options_t *popts,
27 dimm_params_t *pdimm,
28 unsigned int ctrl_num)
29 {
30 /*
31 * Factors to consider for clock adjust:
32 * - number of chips on bus
33 * - position of slot
34 * - DDR1 vs. DDR2?
35 * - ???
36 *
37 * This needs to be determined on a board-by-board basis.
38 * 0110 3/4 cycle late
39 * 0111 7/8 cycle late
40 */
41 popts->clk_adjust = 7;
42
43 /*
44 * Factors to consider for CPO:
45 * - frequency
46 * - ddr1 vs. ddr2
47 */
48 popts->cpo_override = 9;
49
50 /*
51 * Factors to consider for write data delay:
52 * - number of DIMMs
53 *
54 * 1 = 1/4 clock delay
55 * 2 = 1/2 clock delay
56 * 3 = 3/4 clock delay
57 * 4 = 1 clock delay
58 * 5 = 5/4 clock delay
59 * 6 = 3/2 clock delay
60 */
61 popts->write_data_delay = 3;
62
63 /*
64 * Factors to consider for half-strength driver enable:
65 * - number of DIMMs installed
66 */
67 popts->half_strength_driver_enable = 0;
68 }
69