1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
4 * (C) Copyright 2013 - 2018 Xilinx, Inc.
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <log.h>
10 #include <dm/uclass.h>
11 #include <env.h>
12 #include <fdtdec.h>
13 #include <fpga.h>
14 #include <malloc.h>
15 #include <mmc.h>
16 #include <watchdog.h>
17 #include <wdt.h>
18 #include <zynqpl.h>
19 #include <asm/global_data.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/sys_proto.h>
22 #include "../common/board.h"
23
24 DECLARE_GLOBAL_DATA_PTR;
25
board_init(void)26 int board_init(void)
27 {
28 if (IS_ENABLED(CONFIG_SPL_BUILD))
29 printf("Silicon version:\t%d\n", zynq_get_silicon_version());
30
31 return 0;
32 }
33
board_late_init(void)34 int board_late_init(void)
35 {
36 int env_targets_len = 0;
37 const char *mode;
38 char *new_targets;
39 char *env_targets;
40
41 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
42 debug("Saved variables - Skipping\n");
43 return 0;
44 }
45
46 if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
47 return 0;
48
49 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
50 case ZYNQ_BM_QSPI:
51 mode = "qspi";
52 env_set("modeboot", "qspiboot");
53 break;
54 case ZYNQ_BM_NAND:
55 mode = "nand";
56 env_set("modeboot", "nandboot");
57 break;
58 case ZYNQ_BM_NOR:
59 mode = "nor";
60 env_set("modeboot", "norboot");
61 break;
62 case ZYNQ_BM_SD:
63 mode = "mmc0";
64 env_set("modeboot", "sdboot");
65 break;
66 case ZYNQ_BM_JTAG:
67 mode = "jtag pxe dhcp";
68 env_set("modeboot", "jtagboot");
69 break;
70 default:
71 mode = "";
72 env_set("modeboot", "");
73 break;
74 }
75
76 /*
77 * One terminating char + one byte for space between mode
78 * and default boot_targets
79 */
80 env_targets = env_get("boot_targets");
81 if (env_targets)
82 env_targets_len = strlen(env_targets);
83
84 new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
85 if (!new_targets)
86 return -ENOMEM;
87
88 sprintf(new_targets, "%s %s", mode,
89 env_targets ? env_targets : "");
90
91 env_set("boot_targets", new_targets);
92
93 return board_late_init_xilinx();
94 }
95
96 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
dram_init_banksize(void)97 int dram_init_banksize(void)
98 {
99 return fdtdec_setup_memory_banksize();
100 }
101
dram_init(void)102 int dram_init(void)
103 {
104 if (fdtdec_setup_mem_size_base() != 0)
105 return -EINVAL;
106
107 zynq_ddrc_init();
108
109 return 0;
110 }
111 #else
dram_init(void)112 int dram_init(void)
113 {
114 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
115 CONFIG_SYS_SDRAM_SIZE);
116
117 zynq_ddrc_init();
118
119 return 0;
120 }
121 #endif
122