1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2002-2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
10 */
11
12 #include <common.h>
13 #include <bloblist.h>
14 #include <bootstage.h>
15 #include <clock_legacy.h>
16 #include <console.h>
17 #include <cpu.h>
18 #include <cpu_func.h>
19 #include <dm.h>
20 #include <env.h>
21 #include <env_internal.h>
22 #include <fdtdec.h>
23 #include <fs.h>
24 #include <hang.h>
25 #include <i2c.h>
26 #include <init.h>
27 #include <initcall.h>
28 #include <lcd.h>
29 #include <log.h>
30 #include <malloc.h>
31 #include <mapmem.h>
32 #include <os.h>
33 #include <post.h>
34 #include <relocate.h>
35 #include <serial.h>
36 #ifdef CONFIG_SPL
37 #include <spl.h>
38 #endif
39 #include <status_led.h>
40 #include <sysreset.h>
41 #include <timer.h>
42 #include <trace.h>
43 #include <video.h>
44 #include <watchdog.h>
45 #include <asm/cache.h>
46 #ifdef CONFIG_MACH_TYPE
47 #include <asm/mach-types.h>
48 #endif
49 #if defined(CONFIG_MP) && defined(CONFIG_PPC)
50 #include <asm/mp.h>
51 #endif
52 #include <asm/global_data.h>
53 #include <asm/io.h>
54 #include <asm/sections.h>
55 #include <dm/root.h>
56 #include <linux/errno.h>
57
58 /*
59 * Pointer to initial global data area
60 *
61 * Here we initialize it if needed.
62 */
63 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
64 #undef XTRN_DECLARE_GLOBAL_DATA_PTR
65 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
66 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
67 #else
68 DECLARE_GLOBAL_DATA_PTR;
69 #endif
70
71 /*
72 * TODO(sjg@chromium.org): IMO this code should be
73 * refactored to a single function, something like:
74 *
75 * void led_set_state(enum led_colour_t colour, int on);
76 */
77 /************************************************************************
78 * Coloured LED functionality
79 ************************************************************************
80 * May be supplied by boards if desired
81 */
coloured_LED_init(void)82 __weak void coloured_LED_init(void) {}
red_led_on(void)83 __weak void red_led_on(void) {}
red_led_off(void)84 __weak void red_led_off(void) {}
green_led_on(void)85 __weak void green_led_on(void) {}
green_led_off(void)86 __weak void green_led_off(void) {}
yellow_led_on(void)87 __weak void yellow_led_on(void) {}
yellow_led_off(void)88 __weak void yellow_led_off(void) {}
blue_led_on(void)89 __weak void blue_led_on(void) {}
blue_led_off(void)90 __weak void blue_led_off(void) {}
91
92 /*
93 * Why is gd allocated a register? Prior to reloc it might be better to
94 * just pass it around to each function in this file?
95 *
96 * After reloc one could argue that it is hardly used and doesn't need
97 * to be in a register. Or if it is it should perhaps hold pointers to all
98 * global data for all modules, so that post-reloc we can avoid the massive
99 * literal pool we get on ARM. Or perhaps just encourage each module to use
100 * a structure...
101 */
102
103 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
init_func_watchdog_init(void)104 static int init_func_watchdog_init(void)
105 {
106 # if defined(CONFIG_HW_WATCHDOG) && \
107 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
108 defined(CONFIG_SH) || \
109 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
110 defined(CONFIG_IMX_WATCHDOG))
111 hw_watchdog_init();
112 puts(" Watchdog enabled\n");
113 # endif
114 WATCHDOG_RESET();
115
116 return 0;
117 }
118
init_func_watchdog_reset(void)119 int init_func_watchdog_reset(void)
120 {
121 WATCHDOG_RESET();
122
123 return 0;
124 }
125 #endif /* CONFIG_WATCHDOG */
126
board_add_ram_info(int use_default)127 __weak void board_add_ram_info(int use_default)
128 {
129 /* please define platform specific board_add_ram_info() */
130 }
131
init_baud_rate(void)132 static int init_baud_rate(void)
133 {
134 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
135 return 0;
136 }
137
display_text_info(void)138 static int display_text_info(void)
139 {
140 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
141 ulong bss_start, bss_end, text_base;
142
143 bss_start = (ulong)&__bss_start;
144 bss_end = (ulong)&__bss_end;
145
146 #ifdef CONFIG_SYS_TEXT_BASE
147 text_base = CONFIG_SYS_TEXT_BASE;
148 #else
149 text_base = CONFIG_SYS_MONITOR_BASE;
150 #endif
151
152 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
153 text_base, bss_start, bss_end);
154 #endif
155
156 return 0;
157 }
158
159 #ifdef CONFIG_SYSRESET
print_resetinfo(void)160 static int print_resetinfo(void)
161 {
162 struct udevice *dev;
163 char status[256];
164 int ret;
165
166 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
167 if (ret) {
168 debug("%s: No sysreset device found (error: %d)\n",
169 __func__, ret);
170 /* Not all boards have sysreset drivers available during early
171 * boot, so don't fail if one can't be found.
172 */
173 return 0;
174 }
175
176 if (!sysreset_get_status(dev, status, sizeof(status)))
177 printf("%s", status);
178
179 return 0;
180 }
181 #endif
182
183 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
print_cpuinfo(void)184 static int print_cpuinfo(void)
185 {
186 struct udevice *dev;
187 char desc[512];
188 int ret;
189
190 dev = cpu_get_current_dev();
191 if (!dev) {
192 debug("%s: Could not get CPU device\n",
193 __func__);
194 return -ENODEV;
195 }
196
197 ret = cpu_get_desc(dev, desc, sizeof(desc));
198 if (ret) {
199 debug("%s: Could not get CPU description (err = %d)\n",
200 dev->name, ret);
201 return ret;
202 }
203
204 printf("CPU: %s\n", desc);
205
206 return 0;
207 }
208 #endif
209
announce_dram_init(void)210 static int announce_dram_init(void)
211 {
212 puts("DRAM: ");
213 return 0;
214 }
215
show_dram_config(void)216 static int show_dram_config(void)
217 {
218 unsigned long long size;
219 int i;
220
221 debug("\nRAM Configuration:\n");
222 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
223 size += gd->bd->bi_dram[i].size;
224 debug("Bank #%d: %llx ", i,
225 (unsigned long long)(gd->bd->bi_dram[i].start));
226 #ifdef DEBUG
227 print_size(gd->bd->bi_dram[i].size, "\n");
228 #endif
229 }
230 debug("\nDRAM: ");
231
232 print_size(size, "");
233 board_add_ram_info(0);
234 putc('\n');
235
236 return 0;
237 }
238
dram_init_banksize(void)239 __weak int dram_init_banksize(void)
240 {
241 gd->bd->bi_dram[0].start = gd->ram_base;
242 gd->bd->bi_dram[0].size = get_effective_memsize();
243
244 return 0;
245 }
246
247 #if defined(CONFIG_SYS_I2C)
init_func_i2c(void)248 static int init_func_i2c(void)
249 {
250 puts("I2C: ");
251 i2c_init_all();
252 puts("ready\n");
253 return 0;
254 }
255 #endif
256
257 #if defined(CONFIG_VID)
init_func_vid(void)258 __weak int init_func_vid(void)
259 {
260 return 0;
261 }
262 #endif
263
setup_mon_len(void)264 static int setup_mon_len(void)
265 {
266 #if defined(__ARM__) || defined(__MICROBLAZE__)
267 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
268 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
269 gd->mon_len = (ulong)&_end - (ulong)_init;
270 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
271 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
272 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
273 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
274 #elif defined(CONFIG_SYS_MONITOR_BASE)
275 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
276 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
277 #endif
278 return 0;
279 }
280
setup_spl_handoff(void)281 static int setup_spl_handoff(void)
282 {
283 #if CONFIG_IS_ENABLED(HANDOFF)
284 gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
285 sizeof(struct spl_handoff));
286 debug("Found SPL hand-off info %p\n", gd->spl_handoff);
287 #endif
288
289 return 0;
290 }
291
arch_cpu_init(void)292 __weak int arch_cpu_init(void)
293 {
294 return 0;
295 }
296
mach_cpu_init(void)297 __weak int mach_cpu_init(void)
298 {
299 return 0;
300 }
301
302 /* Get the top of usable RAM */
board_get_usable_ram_top(ulong total_size)303 __weak ulong board_get_usable_ram_top(ulong total_size)
304 {
305 #if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0
306 /*
307 * Detect whether we have so much RAM that it goes past the end of our
308 * 32-bit address space. If so, clip the usable RAM so it doesn't.
309 */
310 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
311 /*
312 * Will wrap back to top of 32-bit space when reservations
313 * are made.
314 */
315 return 0;
316 #endif
317 return gd->ram_top;
318 }
319
setup_dest_addr(void)320 static int setup_dest_addr(void)
321 {
322 debug("Monitor len: %08lX\n", gd->mon_len);
323 /*
324 * Ram is setup, size stored in gd !!
325 */
326 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
327 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
328 /*
329 * Subtract specified amount of memory to hide so that it won't
330 * get "touched" at all by U-Boot. By fixing up gd->ram_size
331 * the Linux kernel should now get passed the now "corrected"
332 * memory size and won't touch it either. This should work
333 * for arch/ppc and arch/powerpc. Only Linux board ports in
334 * arch/powerpc with bootwrapper support, that recalculate the
335 * memory size from the SDRAM controller setup will have to
336 * get fixed.
337 */
338 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
339 #endif
340 #ifdef CONFIG_SYS_SDRAM_BASE
341 gd->ram_base = CONFIG_SYS_SDRAM_BASE;
342 #endif
343 gd->ram_top = gd->ram_base + get_effective_memsize();
344 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
345 gd->relocaddr = gd->ram_top;
346 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
347 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
348 /*
349 * We need to make sure the location we intend to put secondary core
350 * boot code is reserved and not used by any part of u-boot
351 */
352 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
353 gd->relocaddr = determine_mp_bootpg(NULL);
354 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
355 }
356 #endif
357 return 0;
358 }
359
360 #ifdef CONFIG_PRAM
361 /* reserve protected RAM */
reserve_pram(void)362 static int reserve_pram(void)
363 {
364 ulong reg;
365
366 reg = env_get_ulong("pram", 10, CONFIG_PRAM);
367 gd->relocaddr -= (reg << 10); /* size is in kB */
368 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
369 gd->relocaddr);
370 return 0;
371 }
372 #endif /* CONFIG_PRAM */
373
374 /* Round memory pointer down to next 4 kB limit */
reserve_round_4k(void)375 static int reserve_round_4k(void)
376 {
377 gd->relocaddr &= ~(4096 - 1);
378 return 0;
379 }
380
arch_reserve_mmu(void)381 __weak int arch_reserve_mmu(void)
382 {
383 return 0;
384 }
385
reserve_video(void)386 static int reserve_video(void)
387 {
388 #ifdef CONFIG_DM_VIDEO
389 ulong addr;
390 int ret;
391
392 addr = gd->relocaddr;
393 ret = video_reserve(&addr);
394 if (ret)
395 return ret;
396 debug("Reserving %luk for video at: %08lx\n",
397 (unsigned long)gd->relocaddr - addr, addr);
398 gd->relocaddr = addr;
399 #elif defined(CONFIG_LCD)
400 # ifdef CONFIG_FB_ADDR
401 gd->fb_base = CONFIG_FB_ADDR;
402 # else
403 /* reserve memory for LCD display (always full pages) */
404 gd->relocaddr = lcd_setmem(gd->relocaddr);
405 gd->fb_base = gd->relocaddr;
406 # endif /* CONFIG_FB_ADDR */
407 #endif
408
409 return 0;
410 }
411
reserve_trace(void)412 static int reserve_trace(void)
413 {
414 #ifdef CONFIG_TRACE
415 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
416 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
417 debug("Reserving %luk for trace data at: %08lx\n",
418 (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
419 #endif
420
421 return 0;
422 }
423
reserve_uboot(void)424 static int reserve_uboot(void)
425 {
426 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
427 /*
428 * reserve memory for U-Boot code, data & bss
429 * round down to next 4 kB limit
430 */
431 gd->relocaddr -= gd->mon_len;
432 gd->relocaddr &= ~(4096 - 1);
433 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
434 /* round down to next 64 kB limit so that IVPR stays aligned */
435 gd->relocaddr &= ~(65536 - 1);
436 #endif
437
438 debug("Reserving %ldk for U-Boot at: %08lx\n",
439 gd->mon_len >> 10, gd->relocaddr);
440 }
441
442 gd->start_addr_sp = gd->relocaddr;
443
444 return 0;
445 }
446
447 /*
448 * reserve after start_addr_sp the requested size and make the stack pointer
449 * 16-byte aligned, this alignment is needed for cast on the reserved memory
450 * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes
451 * = ARMv8 Instruction Set Overview: quad word, 16 bytes
452 */
reserve_stack_aligned(size_t size)453 static unsigned long reserve_stack_aligned(size_t size)
454 {
455 return ALIGN_DOWN(gd->start_addr_sp - size, 16);
456 }
457
458 #ifdef CONFIG_SYS_NONCACHED_MEMORY
reserve_noncached(void)459 static int reserve_noncached(void)
460 {
461 /*
462 * The value of gd->start_addr_sp must match the value of malloc_start
463 * calculated in boatrd_f.c:initr_malloc(), which is passed to
464 * board_r.c:mem_malloc_init() and then used by
465 * cache.c:noncached_init()
466 *
467 * These calculations must match the code in cache.c:noncached_init()
468 */
469 gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
470 MMU_SECTION_SIZE;
471 gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
472 MMU_SECTION_SIZE);
473 debug("Reserving %dM for noncached_alloc() at: %08lx\n",
474 CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
475
476 return 0;
477 }
478 #endif
479
480 /* reserve memory for malloc() area */
reserve_malloc(void)481 static int reserve_malloc(void)
482 {
483 gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN);
484 debug("Reserving %dk for malloc() at: %08lx\n",
485 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
486 #ifdef CONFIG_SYS_NONCACHED_MEMORY
487 reserve_noncached();
488 #endif
489
490 return 0;
491 }
492
493 /* (permanently) allocate a Board Info struct */
reserve_board(void)494 static int reserve_board(void)
495 {
496 if (!gd->bd) {
497 gd->start_addr_sp = reserve_stack_aligned(sizeof(struct bd_info));
498 gd->bd = (struct bd_info *)map_sysmem(gd->start_addr_sp,
499 sizeof(struct bd_info));
500 memset(gd->bd, '\0', sizeof(struct bd_info));
501 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
502 sizeof(struct bd_info), gd->start_addr_sp);
503 }
504 return 0;
505 }
506
reserve_global_data(void)507 static int reserve_global_data(void)
508 {
509 gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t));
510 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
511 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
512 sizeof(gd_t), gd->start_addr_sp);
513 return 0;
514 }
515
reserve_fdt(void)516 static int reserve_fdt(void)
517 {
518 if (!IS_ENABLED(CONFIG_OF_EMBED)) {
519 /*
520 * If the device tree is sitting immediately above our image
521 * then we must relocate it. If it is embedded in the data
522 * section, then it will be relocated with other data.
523 */
524 if (gd->fdt_blob) {
525 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob), 32);
526
527 gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size);
528 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
529 debug("Reserving %lu Bytes for FDT at: %08lx\n",
530 gd->fdt_size, gd->start_addr_sp);
531 }
532 }
533
534 return 0;
535 }
536
reserve_bootstage(void)537 static int reserve_bootstage(void)
538 {
539 #ifdef CONFIG_BOOTSTAGE
540 int size = bootstage_get_size();
541
542 gd->start_addr_sp = reserve_stack_aligned(size);
543 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
544 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
545 gd->start_addr_sp);
546 #endif
547
548 return 0;
549 }
550
arch_reserve_stacks(void)551 __weak int arch_reserve_stacks(void)
552 {
553 return 0;
554 }
555
reserve_stacks(void)556 static int reserve_stacks(void)
557 {
558 /* make stack pointer 16-byte aligned */
559 gd->start_addr_sp = reserve_stack_aligned(16);
560
561 /*
562 * let the architecture-specific code tailor gd->start_addr_sp and
563 * gd->irq_sp
564 */
565 return arch_reserve_stacks();
566 }
567
reserve_bloblist(void)568 static int reserve_bloblist(void)
569 {
570 #ifdef CONFIG_BLOBLIST
571 /* Align to a 4KB boundary for easier reading of addresses */
572 gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp -
573 CONFIG_BLOBLIST_SIZE_RELOC, 0x1000);
574 gd->new_bloblist = map_sysmem(gd->start_addr_sp,
575 CONFIG_BLOBLIST_SIZE_RELOC);
576 #endif
577
578 return 0;
579 }
580
display_new_sp(void)581 static int display_new_sp(void)
582 {
583 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
584
585 return 0;
586 }
587
arch_setup_bdinfo(void)588 __weak int arch_setup_bdinfo(void)
589 {
590 return 0;
591 }
592
setup_bdinfo(void)593 int setup_bdinfo(void)
594 {
595 struct bd_info *bd = gd->bd;
596
597 if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
598 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
599 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
600 }
601
602 #ifdef CONFIG_MACH_TYPE
603 bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
604 #endif
605
606 return arch_setup_bdinfo();
607 }
608
609 #ifdef CONFIG_POST
init_post(void)610 static int init_post(void)
611 {
612 post_bootmode_init();
613 post_run(NULL, POST_ROM | post_bootmode_get(0));
614
615 return 0;
616 }
617 #endif
618
reloc_fdt(void)619 static int reloc_fdt(void)
620 {
621 if (!IS_ENABLED(CONFIG_OF_EMBED)) {
622 if (gd->flags & GD_FLG_SKIP_RELOC)
623 return 0;
624 if (gd->new_fdt) {
625 memcpy(gd->new_fdt, gd->fdt_blob,
626 fdt_totalsize(gd->fdt_blob));
627 gd->fdt_blob = gd->new_fdt;
628 }
629 }
630
631 return 0;
632 }
633
reloc_bootstage(void)634 static int reloc_bootstage(void)
635 {
636 #ifdef CONFIG_BOOTSTAGE
637 if (gd->flags & GD_FLG_SKIP_RELOC)
638 return 0;
639 if (gd->new_bootstage) {
640 int size = bootstage_get_size();
641
642 debug("Copying bootstage from %p to %p, size %x\n",
643 gd->bootstage, gd->new_bootstage, size);
644 memcpy(gd->new_bootstage, gd->bootstage, size);
645 gd->bootstage = gd->new_bootstage;
646 bootstage_relocate();
647 }
648 #endif
649
650 return 0;
651 }
652
reloc_bloblist(void)653 static int reloc_bloblist(void)
654 {
655 #ifdef CONFIG_BLOBLIST
656 if (gd->flags & GD_FLG_SKIP_RELOC)
657 return 0;
658 if (gd->new_bloblist) {
659 int size = CONFIG_BLOBLIST_SIZE;
660
661 debug("Copying bloblist from %p to %p, size %x\n",
662 gd->bloblist, gd->new_bloblist, size);
663 bloblist_reloc(gd->new_bloblist, CONFIG_BLOBLIST_SIZE_RELOC,
664 gd->bloblist, size);
665 gd->bloblist = gd->new_bloblist;
666 }
667 #endif
668
669 return 0;
670 }
671
setup_reloc(void)672 static int setup_reloc(void)
673 {
674 if (gd->flags & GD_FLG_SKIP_RELOC) {
675 debug("Skipping relocation due to flag\n");
676 return 0;
677 }
678
679 #ifdef CONFIG_SYS_TEXT_BASE
680 #ifdef ARM
681 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
682 #elif defined(CONFIG_M68K)
683 /*
684 * On all ColdFire arch cpu, monitor code starts always
685 * just after the default vector table location, so at 0x400
686 */
687 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
688 #elif !defined(CONFIG_SANDBOX)
689 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
690 #endif
691 #endif
692 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
693
694 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
695 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
696 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
697 gd->start_addr_sp);
698
699 return 0;
700 }
701
702 #ifdef CONFIG_OF_BOARD_FIXUP
fix_fdt(void)703 static int fix_fdt(void)
704 {
705 return board_fix_fdt((void *)gd->fdt_blob);
706 }
707 #endif
708
709 /* ARM calls relocate_code from its crt0.S */
710 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
711 !CONFIG_IS_ENABLED(X86_64)
712
jump_to_copy(void)713 static int jump_to_copy(void)
714 {
715 if (gd->flags & GD_FLG_SKIP_RELOC)
716 return 0;
717 /*
718 * x86 is special, but in a nice way. It uses a trampoline which
719 * enables the dcache if possible.
720 *
721 * For now, other archs use relocate_code(), which is implemented
722 * similarly for all archs. When we do generic relocation, hopefully
723 * we can make all archs enable the dcache prior to relocation.
724 */
725 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
726 /*
727 * SDRAM and console are now initialised. The final stack can now
728 * be setup in SDRAM. Code execution will continue in Flash, but
729 * with the stack in SDRAM and Global Data in temporary memory
730 * (CPU cache)
731 */
732 arch_setup_gd(gd->new_gd);
733 board_init_f_r_trampoline(gd->start_addr_sp);
734 #else
735 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
736 #endif
737
738 return 0;
739 }
740 #endif
741
742 /* Record the board_init_f() bootstage (after arch_cpu_init()) */
initf_bootstage(void)743 static int initf_bootstage(void)
744 {
745 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
746 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
747 int ret;
748
749 ret = bootstage_init(!from_spl);
750 if (ret)
751 return ret;
752 if (from_spl) {
753 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
754 CONFIG_BOOTSTAGE_STASH_SIZE);
755
756 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
757 if (ret && ret != -ENOENT) {
758 debug("Failed to unstash bootstage: err=%d\n", ret);
759 return ret;
760 }
761 }
762
763 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
764
765 return 0;
766 }
767
initf_dm(void)768 static int initf_dm(void)
769 {
770 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
771 int ret;
772
773 bootstage_start(BOOTSTAGE_ID_ACCUM_DM_F, "dm_f");
774 ret = dm_init_and_scan(true);
775 bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_F);
776 if (ret)
777 return ret;
778
779 if (IS_ENABLED(CONFIG_TIMER_EARLY)) {
780 ret = dm_timer_init();
781 if (ret)
782 return ret;
783 }
784 #endif
785
786 return 0;
787 }
788
789 /* Architecture-specific memory reservation */
reserve_arch(void)790 __weak int reserve_arch(void)
791 {
792 return 0;
793 }
794
arch_cpu_init_dm(void)795 __weak int arch_cpu_init_dm(void)
796 {
797 return 0;
798 }
799
checkcpu(void)800 __weak int checkcpu(void)
801 {
802 return 0;
803 }
804
clear_bss(void)805 __weak int clear_bss(void)
806 {
807 return 0;
808 }
809
810 static const init_fnc_t init_sequence_f[] = {
811 setup_mon_len,
812 #ifdef CONFIG_OF_CONTROL
813 fdtdec_setup,
814 #endif
815 #ifdef CONFIG_TRACE_EARLY
816 trace_early_init,
817 #endif
818 initf_malloc,
819 log_init,
820 initf_bootstage, /* uses its own timer, so does not need DM */
821 #ifdef CONFIG_BLOBLIST
822 bloblist_init,
823 #endif
824 setup_spl_handoff,
825 #if defined(CONFIG_CONSOLE_RECORD_INIT_F)
826 console_record_init,
827 #endif
828 #if defined(CONFIG_HAVE_FSP)
829 arch_fsp_init,
830 #endif
831 arch_cpu_init, /* basic arch cpu dependent setup */
832 mach_cpu_init, /* SoC/machine dependent CPU setup */
833 initf_dm,
834 arch_cpu_init_dm,
835 #if defined(CONFIG_BOARD_EARLY_INIT_F)
836 board_early_init_f,
837 #endif
838 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
839 /* get CPU and bus clocks according to the environment variable */
840 get_clocks, /* get CPU and bus clocks (etc.) */
841 #endif
842 #if !defined(CONFIG_M68K)
843 timer_init, /* initialize timer */
844 #endif
845 #if defined(CONFIG_BOARD_POSTCLK_INIT)
846 board_postclk_init,
847 #endif
848 env_init, /* initialize environment */
849 init_baud_rate, /* initialze baudrate settings */
850 serial_init, /* serial communications setup */
851 console_init_f, /* stage 1 init of console */
852 display_options, /* say that we are here */
853 display_text_info, /* show debugging info if required */
854 checkcpu,
855 #if defined(CONFIG_SYSRESET)
856 print_resetinfo,
857 #endif
858 #if defined(CONFIG_DISPLAY_CPUINFO)
859 print_cpuinfo, /* display cpu info (and speed) */
860 #endif
861 #if defined(CONFIG_DTB_RESELECT)
862 embedded_dtb_select,
863 #endif
864 #if defined(CONFIG_DISPLAY_BOARDINFO)
865 show_board_info,
866 #endif
867 INIT_FUNC_WATCHDOG_INIT
868 #if defined(CONFIG_MISC_INIT_F)
869 misc_init_f,
870 #endif
871 INIT_FUNC_WATCHDOG_RESET
872 #if defined(CONFIG_SYS_I2C)
873 init_func_i2c,
874 #endif
875 #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
876 init_func_vid,
877 #endif
878 announce_dram_init,
879 dram_init, /* configure available RAM banks */
880 #ifdef CONFIG_POST
881 post_init_f,
882 #endif
883 INIT_FUNC_WATCHDOG_RESET
884 #if defined(CONFIG_SYS_DRAM_TEST)
885 testdram,
886 #endif /* CONFIG_SYS_DRAM_TEST */
887 INIT_FUNC_WATCHDOG_RESET
888
889 #ifdef CONFIG_POST
890 init_post,
891 #endif
892 INIT_FUNC_WATCHDOG_RESET
893 /*
894 * Now that we have DRAM mapped and working, we can
895 * relocate the code and continue running from DRAM.
896 *
897 * Reserve memory at end of RAM for (top down in that order):
898 * - area that won't get touched by U-Boot and Linux (optional)
899 * - kernel log buffer
900 * - protected RAM
901 * - LCD framebuffer
902 * - monitor code
903 * - board info struct
904 */
905 setup_dest_addr,
906 #ifdef CONFIG_OF_BOARD_FIXUP
907 fix_fdt,
908 #endif
909 #ifdef CONFIG_PRAM
910 reserve_pram,
911 #endif
912 reserve_round_4k,
913 arch_reserve_mmu,
914 reserve_video,
915 reserve_trace,
916 reserve_uboot,
917 reserve_malloc,
918 reserve_board,
919 reserve_global_data,
920 reserve_fdt,
921 reserve_bootstage,
922 reserve_bloblist,
923 reserve_arch,
924 reserve_stacks,
925 dram_init_banksize,
926 show_dram_config,
927 INIT_FUNC_WATCHDOG_RESET
928 setup_bdinfo,
929 display_new_sp,
930 INIT_FUNC_WATCHDOG_RESET
931 reloc_fdt,
932 reloc_bootstage,
933 reloc_bloblist,
934 setup_reloc,
935 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
936 copy_uboot_to_ram,
937 do_elf_reloc_fixups,
938 #endif
939 clear_bss,
940 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
941 !CONFIG_IS_ENABLED(X86_64)
942 jump_to_copy,
943 #endif
944 NULL,
945 };
946
board_init_f(ulong boot_flags)947 void board_init_f(ulong boot_flags)
948 {
949 gd->flags = boot_flags;
950 gd->have_console = 0;
951
952 if (initcall_run_list(init_sequence_f))
953 hang();
954
955 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
956 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
957 !defined(CONFIG_ARC)
958 /* NOTREACHED - jump_to_copy() does not return */
959 hang();
960 #endif
961 }
962
963 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
964 /*
965 * For now this code is only used on x86.
966 *
967 * init_sequence_f_r is the list of init functions which are run when
968 * U-Boot is executing from Flash with a semi-limited 'C' environment.
969 * The following limitations must be considered when implementing an
970 * '_f_r' function:
971 * - 'static' variables are read-only
972 * - Global Data (gd->xxx) is read/write
973 *
974 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
975 * supported). It _should_, if possible, copy global data to RAM and
976 * initialise the CPU caches (to speed up the relocation process)
977 *
978 * NOTE: At present only x86 uses this route, but it is intended that
979 * all archs will move to this when generic relocation is implemented.
980 */
981 static const init_fnc_t init_sequence_f_r[] = {
982 #if !CONFIG_IS_ENABLED(X86_64)
983 init_cache_f_r,
984 #endif
985
986 NULL,
987 };
988
board_init_f_r(void)989 void board_init_f_r(void)
990 {
991 if (initcall_run_list(init_sequence_f_r))
992 hang();
993
994 /*
995 * The pre-relocation drivers may be using memory that has now gone
996 * away. Mark serial as unavailable - this will fall back to the debug
997 * UART if available.
998 *
999 * Do the same with log drivers since the memory may not be available.
1000 */
1001 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
1002 #ifdef CONFIG_TIMER
1003 gd->timer = NULL;
1004 #endif
1005
1006 /*
1007 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1008 * Transfer execution from Flash to RAM by calculating the address
1009 * of the in-RAM copy of board_init_r() and calling it
1010 */
1011 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
1012
1013 /* NOTREACHED - board_init_r() does not return */
1014 hang();
1015 }
1016 #endif /* CONFIG_X86 */
1017