1.. SPDX-License-Identifier: GPL-2.0+
2
3MIPS
4====
5
6Notes for the MIPS architecture port of U-Boot
7
8Toolchains
9----------
10
11  * `ELDK < DULG < DENX <http://www.denx.de/wiki/DULG/ELDK>`_
12  * `Embedded Debian -- Cross-development toolchains <http://www.emdebian.org/crosstools.html>`_
13  * `Buildroot <http://buildroot.uclibc.org/>`_
14
15Known Issues
16------------
17
18  * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
19
20    Cache will be disabled before entering the loaded ELF image without
21    writing back and invalidating cache lines. This leads to cache
22    incoherency in most cases, unless the code gets loaded after U-Boot
23    re-initializes the cache. The more common uImage 'bootm' command does
24    not suffer this problem.
25
26    [workaround] To avoid this cache incoherency:
27       - insert flush_cache(all) before calling dcache_disable(), or
28       - fix dcache_disable() to do both flushing and disabling cache.
29
30  * Note that Linux users need to kill dcache_disable() in do_bootelf_exec()
31    or override do_bootelf_exec() not to disable I-/D-caches, because most
32    Linux/MIPS ports don't re-enable caches after entering kernel_entry.
33
34TODOs
35-----
36
37  * Probe CPU types, I-/D-cache and TLB size etc. automatically
38  * Secondary cache support missing
39  * Initialize TLB entries redardless of their use
40  * R2000/R3000 class parts are not supported
41  * Limited testing across different MIPS variants
42  * Due to cache initialization issues, the DRAM on board must be
43    initialized in board specific assembler language before the cache init
44    code is run -- that is, initialize the DRAM in lowlevel_init().
45  * centralize/share more CPU code of MIPS32, MIPS64 and XBurst
46  * support Qemu Malta
47