1.. SPDX-License-Identifier: GPL-2.0+
2
3NDS32
4=====
5
6NDS32 is a new high-performance 32-bit RISC microprocessor core.
7
8http://www.andestech.com/
9
10AndeStar ISA
11------------
12AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
13achieve optimal system performance, code density, and power efficiency.
14
15It contains the following features:
16 - Intermixable 32-bit and 16-bit instruction sets without the need for
17   mode switch.
18 - 16-bit instructions as a frequently used subset of 32-bit instructions.
19 - RISC-style register-based instruction set.
20 - 32 32-bit General Purpose Registers (GPR).
21 - Upto 1024 User Special Registers (USR) for existing and extension
22   instructions.
23 - Rich load/store instructions for...
24      - Single memory access with base address update.
25      - Multiple aligned and unaligned memory accesses for memory copy and stack
26        operations.
27      - Data prefetch to improve data cache performance.
28      - Non-bus locking synchronization instructions.
29 - PC relative jump and PC read instructions for efficient position independent
30   code.
31 - Multiply-add and multiple-sub with 64-bit accumulator.
32 - Instruction for efficient power management.
33 - Bi-endian support.
34 - Three instruction extension space for application acceleration:
35      - Performance extension.
36      - Andes future extensions (for floating-point, multimedia, etc.)
37      - Customer extensions.
38
39AndesCore CPU
40-------------
41Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
42
43For details about N12 CPU family, please check below N1213 features.
44N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
45
46N1213 Features
47^^^^^^^^^^^^^^
48
49CPU Core
50 - 16-/32-bit mixable instruction format.
51 - 32 general-purpose 32-bit registers.
52 - 8-stage pipeline.
53 - Dynamic branch prediction.
54 - 32/64/128/256 BTB.
55 - Return address stack (RAS).
56 - Vector interrupts for internal/external.
57   interrupt controller with 6 hardware interrupt signals.
58 - 3 HW-level nested interruptions.
59 - User and super-user mode support.
60 - Memory-mapped I/O.
61 - Address space up to 4GB.
62
63Memory Management Unit
64 - TLB
65      - 4/8-entry fully associative iTLB/dTLB.
66      - 32/64/128-entry 4-way set-associati.ve main TLB.
67      - TLB locking support
68 - Optional hardware page table walker.
69 - Two groups of page size support.
70     - 4KB & 1MB.
71     - 8KB & 1MB.
72
73Memory Subsystem
74 - I & D cache.
75      - Virtually indexed and physically tagged.
76      - Cache size: 8KB/16KB/32KB/64KB.
77      - Cache line size: 16B/32B.
78      - Set associativity: 2-way, 4-way or direct-mapped.
79      - Cache locking support.
80 - I & D local memory (LM).
81      - Size: 4KB to 1MB.
82      - Bank numbers: 1 or 2.
83      - Optional 1D/2D DMA engine.
84      - Internal or external to CPU core.
85
86Bus Interface
87 - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
88 - Synchronous High speed memory port.
89   (HSMP): 0, 1 or 2 ports.
90
91Debug
92 - JTAG debug interface.
93 - Embedded debug module (EDM).
94 - Optional embedded program tracer interface.
95
96Miscellaneous
97 - Programmable data endian control.
98 - Performance monitoring mechanism.
99
100The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and other
101associated software are actively supported by Andes Technology Corporation.
102