1.. SPDX-License-Identifier: GPL-2.0+
2
3Summary
4=======
5
6The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72
7processor module with an on-chip 6-port TSN switch and a 3D GPU.
8
9
10Quickstart
11==========
12
13Compile U-Boot
14--------------
15
16Configure and compile the binary::
17
18 $ make kontron_sl28_defconfig
19 $ CROSS_COMPILE=aarch64-linux-gnu make
20
21Copy u-boot.rom to a TFTP server.
22
23Install the bootloader on the board
24-----------------------------------
25
26Please note, this bootloader doesn't support the builtin watchdog (yet),
27therefore you have to disable it, see below. Otherwise you'll end up in
28the failsafe bootloader on every reset::
29
30 > tftp path/to/u-boot.rom
31 > sf probe 0
32 > sf update $fileaddr 0x210000 $filesize
33
34The board is fully failsafe, you can't break anything. But because you've
35disabled the builtin watchdog you might have to manually enter failsafe
36mode by asserting the ``FORCE_RECOV#`` line during board reset.
37
38Disable the builtin watchdog
39----------------------------
40
41- boot into the failsafe bootloader, either by asserting the
42  ``FORCE_RECOV#`` line or if you still have the original bootloader
43  installed you can use the command::
44
45  > wdt dev cpld_watchdog@4a; wdt expire 1
46
47- in the failsafe bootloader use the "sl28 nvm" command to disable
48  the automatic start of the builtin watchdog::
49
50  > sl28 nvm 0008
51
52- power-cycle the board
53
54
55Useful I2C tricks
56=================
57
58The board has a board management controller which is not supported in
59u-boot (yet). But you can use the i2c command to access it.
60
61- reset into failsafe bootloader::
62
63  > i2c mw 4a 5.1 0; i2c mw 4a 6.1 6b; i2c mw 4a 4.1 42
64
65- read board management controller version::
66
67  > i2c md 4a 3.1 1
68
69
70Non-volatile Board Configuration Bits
71=====================================
72
73The board has 16 configuration bits which are stored in the CPLD and are
74non-volatile. These can be changed by the `sl28 nvm` command.
75
76===  ===============================================================
77Bit  Description
78===  ===============================================================
79  0  Power-on inhibit
80  1  Enable eMMC boot
81  2  Enable watchdog by default
82  3  Disable failsafe watchdog by default
83  4  Clock generator selection bit 0
84  5  Clock generator selection bit 1
85  6  Disable CPU SerDes clock #2 and PCIe-A clock output
86  7  Disable PCIe-B and PCIe-C clock output
87  8  Keep onboard PHYs in reset
88  9  Keep USB hub in reset
89 10  Keep eDP-to-LVDS converter in reset
90 11  Enable I2C stuck recovery on I2C PM and I2C GP busses
91 12  Enable automatic onboard PHY H/W reset
92 13  reserved
93 14  Used by the RCW to determine boot source
94 15  Used by the RCW to determine boot source
95===  ===============================================================
96
97Please note, that if the board is in failsafe mode, the bits will have the
98factory defaults, ie. all bits are off.
99
100Power-On Inhibit
101----------------
102
103If this is set, the board doesn't automatically turn on when power is
104applied. Instead, the user has to either toggle the ``PWR_BTN#`` line or
105use any other wake-up source such as RTC alarm or Wake-on-LAN.
106
107eMMC Boot
108---------
109
110If this is set, the RCW will be fetched from the on-board eMMC at offset
1111MiB. For further details, have a look at the `Reset Configuration Word
112Documentation`_.
113
114Watchdog
115--------
116
117By default, the CPLD watchdog is enabled in failsafe mode. Using bits 2 and
1183, the user can change its mode or disable it altogether.
119
120=====  =====  ===============================
121Bit 2  Bit 3  Description
122=====  =====  ===============================
123    0      0  Watchdog enabled, failsafe mode
124    0      1  Watchdog disabled
125    1      0  Watchdog enabled, failsafe mode
126    1      1  Watchdog enabled, normal mode
127=====  =====  ===============================
128
129Clock Generator Select
130----------------------
131
132The board is prepared to supply different SerDes clock speeds. But for now,
133only setting 0 is supported, otherwise the CPU will hang because the PLL
134will not lock.
135
136Clock Output Disable And Keep Devices In Reset
137----------------------------------------------
138
139To safe power, the user might disable different devices and clock output of
140the board. It is not supported to disable the "CPU SerDes clock #2" for
141now, otherwise the CPU will hang because the PLL will not lock.
142
143Automatic reset of the onboard PHYs
144-----------------------------------
145
146By default, there is no hardware reset of the onboard PHY. This is because
147for Wake-on-LAN, some registers have to retain their values. If you don't
148use the WOL feature and a soft reset of the PHY is not enough you can
149enable the hardware reset. The onboard PHY hardware reset follows the
150power-on reset.
151
152
153Further documentation
154=====================
155
156- `Vendor Documentation`_
157- `Reset Configuration Word Documentation`_
158
159.. _Reset Configuration Word Documentation: https://raw.githubusercontent.com/kontron/rcw-smarc-sal28/master/README.md
160.. _Vendor Documentation: https://raw.githubusercontent.com/kontron/u-boot-smarc-sal28/master/board/kontron/sl28/README.md
161