1* Intel FSP-M configuration
2
3Several Intel platforms require the execution of the Intel FSP (Firmware
4Support Package) for initialization. The FSP consists of multiple parts, one
5of which is the FSP-M (Memory initialization phase).
6
7This binding applies to the FSP-M for the Intel Apollo Lake SoC.
8
9The FSP-M is available on Github [1].
10For detailed information on the FSP-M parameters see the documentation in
11FSP/ApolloLakeFspBinPkg/Docs [2].
12
13The properties of this binding are all optional. If no properties are set the
14values of the FSP-M are used.
15
16[1] https://github.com/IntelFsp/FSP
17[2] https://github.com/IntelFsp/FSP/tree/master/ApolloLakeFspBinPkg/Docs
18
19Optional properties:
20- fspm,training-delay: Time taken to train DDR memory if there is no cached MRC
21    data, in seconds. This is used to show a message if possible. For Chromebook
22    Coral this is typically 21 seconds. For an APL board with 1GB of RAM, it may
23    be only 6 seconds.
24- fspm,serial-debug-port-address: Debug Serial Port Base address
25- fspm,serial-debug-port-type: Debug Serial Port Type
26  0: NONE
27  1: I/O
28  2: MMIO (default)
29- fspm,serial-debug-port-device: Serial Port Debug Device
30  0: SOC UART0
31  1: SOC UART1
32  2: SOC UART2 (default)
33  3: External Device
34- fspm,serial-debug-port-stride-size: Debug Serial Port Stride Size
35  0: 1
36  2: 4 (default)
37- fspm,mrc-fast-boot: Memory Fast Boot
38- fspm,igd: Integrated Graphics Device
39- fspm,igd-dvmt50-pre-alloc: DVMT Pre-Allocated
40  0x02: 64 MB (default)
41  0x03: 96 MB
42  0x04: 128 MB
43  0x05: 160 MB
44  0x06: 192 MB
45  0x07: 224 MB
46  0x08: 256 MB
47  0x09: 288 MB
48  0x0A: 320 MB
49  0x0B: 352 MB
50  0x0C: 384 MB
51  0x0D: 416 MB
52  0x0E: 448 MB
53  0x0F: 480 MB
54  0x10: 512 MB
55- fspm,aperture-size: Aperture Size
56  0x1: 128 MB (default)
57  0x2: 256 MB
58  0x3: 512 MB
59- fspm,gtt-size: GTT Size
60  0x1: 2 MB
61  0x2: 4 MB
62  0x3: 8 MB (default)
63- fspm,primary-video-adaptor: Primary Display
64  0x0: AUTO (default)
65  0x2: IGD
66  0x3: PCI
67- fspm,package: Package
68  0x0: SODIMM (default)
69  0x1: BGA
70  0x2: BGA mirrored (LPDDR3 only)
71  0x3: SODIMM/UDIMM with Rank 1 Mirrored (DDR3L)
72- fspm,profile: Profile
73  0x01: WIO2_800_7_8_8
74  0x02: WIO2_1066_9_10_10
75  0x03: LPDDR3_1066_8_10_10
76  0x04: LPDDR3_1333_10_12_12
77  0x05: LPDDR3_1600_12_15_15
78  0x06: LPDDR3_1866_14_17_17
79  0x07: LPDDR3_2133_16_20_20
80  0x08: LPDDR4_1066_10_10_10
81  0x09: LPDDR4_1600_14_15_15
82  0x0A: LPDDR4_2133_20_20_20
83  0x0B: LPDDR4_2400_24_22_22
84  0x0C: LPDDR4_2666_24_24_24
85  0x0D: LPDDR4_2933_28_27_27
86  0x0E: LPDDR4_3200_28_29_29
87  0x0F: DDR3_1066_6_6_6
88  0x10: DDR3_1066_7_7_7
89  0x11: DDR3_1066_8_8_8
90  0x12: DDR3_1333_7_7_7
91  0x13: DDR3_1333_8_8_8
92  0x14: DDR3_1333_9_9_9
93  0x15: DDR3_1333_10_10_10
94  0x16: DDR3_1600_8_8_8
95  0x17: DDR3_1600_9_9_9
96  0x18: DDR3_1600_10_10_10
97  0x19: DDR3_1600_11_11_11 (default)
98  0x1A: DDR3_1866_10_10_10
99  0x1B: DDR3_1866_11_11_11
100  0x1C: DDR3_1866_12_12_12
101  0x1D: DDR3_1866_13_13_13
102  0x1E: DDR3_2133_11_11_11
103  0x1F: DDR3_2133_12_12_12
104  0x20: DDR3_2133_13_13_13
105  0x21: DDR3_2133_14_14_14
106  0x22: DDR4_1333_10_10_10
107  0x23: DDR4_1600_10_10_10
108  0x24: DDR4_1600_11_11_11
109  0x25: DDR4_1600_12_12_12
110  0x26: DDR4_1866_12_12_12
111  0x27: DDR4_1866_13_13_13
112  0x28: DDR4_1866_14_14_14
113  0x29: DDR4_2133_14_14_14
114  0x2A: DDR4_2133_15_15_15
115  0x2B: DDR4_2133_16_16_16
116  0x2C: DDR4_2400_15_15_15
117  0x2D: DDR4_2400_16_16_16
118  0x2E: DDR4_2400_17_17_17
119  0x2F: DDR4_2400_18_18_18
120- fspm,memory-down: Memory Down
121  0x0: No (default)
122  0x1: Yes
123  0x2: 1MD+SODIMM (for DDR3L only) ACRD
124  0x3: 1x32 LPDDR4
125- fspm,ddr3l-page-size: DDR3LPageSize
126  0x1: 1KB (default)
127  0x2: 2KB
128- fspm,ddr3-lasr: DDR3LASR
129- fspm,scrambler-support: ScramblerSupport
130- fspm,interleaved-mode: InterleavedMode
131- fspm,channel-hash-mask: ChannelHashMask
132- fspm,fspm,slice-hash-mask: SliceHashMask
133- fspm,channels-slices-enable: ChannelsSlices
134- fspm,min-ref-rate2x-enable: MinRefRate2x
135- fspm,dual-rank-support-enable: DualRankSupport
136- fspm,rmt-mode: RmtMode
137- fspm,memory-size-limit: MemorySizeLimit
138- fspm,low-memory-max-value: LowMemoryMaxValue
139- fspm,high-memory-max-value: HighMemoryMaxValue
140- fspm,disable-fast-boot: FastBoot
141- fspm,dimm0-spd-address: DIMM0 SPD Address
142- fspm,dimm1-spd-address: DIMM1 SPD Address
143- fspm,chX-rank-enable: Must be set to enable rank (X = 0-3)
144- fspm,chX-device-width: DRAM device width per DRAM channel (X = 0-3)
145  0: x8
146  1: x16
147  2: x32
148  3: x64
149- fspm,chX-dram-density: Must specify the DRAM device density (X = 0-3)
150  0: 4Gb
151  1: 6Gb
152  2: 8Gb
153  3: 12Gb
154  4: 16Gb
155  5: 2Gb
156- fspm,chX-option: Channel options (X = 0-3)
157- fspm,chX-odt-config: Channel Odt Config (X = 0-3)
158- fspm,chX-mode2-n: Force 2N Mode (X = 0-3)
159  0x0: Auto
160  0x1: Force 2N CMD Timing Mode
161- fspm,chX-odt-levels: Channel Odt Levels (X = 0-3)
162  0: ODT Connected to SoC
163  1: ODT held high
164- fspm,rmt-check-run: RmtCheckRun
165- fspm,rmt-margin-check-scale-high-threshold: RmtMarginCheckScaleHighThreshold
166- fspm,ch-bit-swizzling: Bit_swizzling
167- fspm,msg-level-mask: MsgLevelMask
168- fspm,pre-mem-gpio-table-pin-num: PreMem GPIO Pin Number for each table
169- fspm,pre-mem-gpio-table-ptr: PreMem GPIO Table Pointer
170- fspm,pre-mem-gpio-table-entry-num: PreMem GPIO Table Entry Number
171- fspm,enhance-port8xh-decoding: Enhance the port 8xh decoding
172- fspm,spd-write-enable: SPD Data Write
173- fspm,mrc-data-saving: MRC Training Data Saving
174- fspm,oem-loading-base: OEM File Loading Address
175- fspm,oem-file-name: OEM File Name to Load
176- fspm,mrc-boot-data-ptr:
177- fspm,emmc-trace-len: eMMC Trace Length
178  0x0: Long
179  0x1: Short
180- fspm,skip-cse-rbp: Skip CSE RBP to support zero sized IBB
181- fspm,npk-en: Npk Enable
182   0: Disable
183   1: Enable
184   2: Debugger
185   3: Auto (default)
186- fspm,fw-trace-en: FW Trace Enable
187- fspm,fw-trace-destination: FW Trace Destination
188  1: NPK_TRACE_TO_MEMORY
189  2: NPK_TRACE_TO_DCI
190  3: NPK_TRACE_TO_BSSB
191  4: NPK_TRACE_TO_PTI (default)
192- fspm,recover-dump: NPK Recovery Dump
193- fspm,msc0-wrap: Memory Region 0 Buffer WrapAround
194  0: n0-warp
195  1: n1-warp (default)
196- fspm,msc1-wrap: Memory Region 1 Buffer WrapAround
197  0: n0-warp
198  1: n1-warp (default)
199- fspm,msc0-size: Memory Region 0 Buffer Size
200  0: 0MB (default)
201  1: 1MB
202  2: 8MB
203  3: 64MB
204  4: 128MB
205  5: 256MB
206  6: 512MB
207  7: 1GB
208- fspm,msc1-size: Memory Region 1 Buffer Size
209  0: 0MB (default)
210  1: 1MB
211  2: 8MB
212  3: 64MB
213  4: 128MB
214  5: 256MB
215  6: 512MB
216  7: 1GB
217- fspm,pti-mode: PTI Mode
218  0: 0ff
219  1: x4 (default)
220  2: x8
221  3: x12
222  4: x16
223- fspm,pti-training: PTI Training
224  0: off (default)
225  1-6: 1-6
226- fspm,pti-speed:
227  0: full
228  1: half
229  2: quarter (default)
230- fspm,punit-mlvl: Punit Message Level
231  0:
232  1: (default)
233  2-4: 2-4
234- fspm,pmc-mlvl: PMC Message Level
235  0:
236  1: (default)
237  2-4: 2-4
238- fspm,sw-trace-en: SW Trace Enable
239- fspm,periodic-retraining-disable: Periodic Retraining Disable
240- fspm,enable-reset-system: Enable Reset System
241- fspm,enable-s3-heci2: Enable HECI2 in S3 resume path
242- fspm,variable-nvs-buffer-ptr:
243- fspm,start-timer-ticker-of-pfet-assert: PCIE SLOT Power Enable Assert Time - PFET
244- fspm,rt-en: Real Time Enabling
245- fspm,skip-pcie-power-sequence: Skip Pcie Power Sequence
246
247Example:
248
249&host_bridge {
250	fspm,package = <PACKAGE_BGA>;
251	fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>;
252	fspm,memory-down = <MEMORY_DOWN_YES>;
253	fspm,scrambler-support = <1>;
254	fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>;
255	fspm,channel-hash-mask = <0x36>;
256	fspm,slice-hash-mask = <0x9>;
257	fspm,low-memory-max-value = <2048>;
258	fspm,ch0-rank-enable = <1>;
259	fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>;
260	fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>;
261	fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING |
262			   CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
263	fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
264	fspm,ch1-rank-enable = <1>;
265	fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>;
266	fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>;
267	fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING |
268			   CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
269	fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
270	fspm,ch2-rank-enable = <1>;
271	fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>;
272	fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>;
273	fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING |
274			   CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
275	fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
276	fspm,ch3-rank-enable = <1>;
277	fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>;
278	fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>;
279	fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING |
280			   CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
281	fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
282	fspm,fspm,skip-cse-rbp = <1>;
283
284	fspm,ch-bit-swizzling = /bits/ 8 <
285		/* LP4_PHYS_CH0A */
286
287		/* DQA[0:7] pins of LPDDR4 module */
288		6 7 5 4 3 1 0 2
289		/* DQA[8:15] pins of LPDDR4 module */
290		12 10 11 13 14 8 9 15
291		/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
292		16 22 23 20 18 17 19 21
293		/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
294		30 28 29 25 24 26 27 31
295
296		/* LP4_PHYS_CH0B */
297		/* DQA[0:7] pins of LPDDR4 module */
298		7 3 5 2 6 0 1 4
299		/* DQA[8:15] pins of LPDDR4 module */
300		 9 14 12 13 10 11 8 15
301		/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
302		20 22 23 16 19 17 18 21
303		/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
304		28 24 26 27 29 30 31 25
305
306		/* LP4_PHYS_CH1A */
307
308		/* DQA[0:7] pins of LPDDR4 module */
309		2 1 6 7 5 4 3 0
310		/* DQA[8:15] pins of LPDDR4 module */
311		11 10 8 9 12 15 13 14
312		/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
313		17 23 19 16 21 22 20 18
314		/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
315		31 29 26 25 28 27 24 30
316
317		/* LP4_PHYS_CH1B */
318
319		/* DQA[0:7] pins of LPDDR4 module */
320		4 3 7 5 6 1 0 2
321		/* DQA[8:15] pins of LPDDR4 module */
322		15 9 8 11 14 13 12 10
323		/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
324		20 23 22 21 18 19 16 17
325		/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
326		25 28 30 31 26 27 24 29>;
327};
328