1MediaTek Gen2 PCIe controller
2
3Required properties:
4- compatible: Should contain one of the following strings:
5	"mediatek,mt7623-pcie"
6- device_type: Must be "pci"
7- reg: Base addresses and lengths of the PCIe subsys and root ports.
8- reg-names: Names of the above areas to use during resource lookup.
9- #address-cells: Address representation for root ports (must be 3)
10- #size-cells: Size representation for root ports (must be 2)
11- clocks: Must contain an entry for each entry in clock-names.
12- clock-names:
13  Mandatory entries:
14   - sys_ckN :transaction layer and data link layer clock
15  Required entries for MT7623:
16   - free_ck :for reference clock of PCIe subsys
17  where N starting from 0 to one less than the number of root ports.
18- phys: List of PHY specifiers (used by generic PHY framework).
19- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
20  number of PHYs as specified in *phys* property.
21- power-domains: A phandle and power domain specifier pair to the power domain
22  which is responsible for collapsing and restoring power to the peripheral.
23- bus-range: Range of bus numbers associated with this controller.
24- ranges: Ranges for the PCI memory and I/O regions.
25
26Required properties for MT7623:
27- #interrupt-cells: Size representation for interrupts (must be 1)
28- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
29  Please refer to the standard PCI bus binding document for a more detailed
30  explanation.
31- resets: Must contain an entry for each entry in reset-names.
32- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
33  number of root ports.
34
35In addition, the device tree node must have sub-nodes describing each
36PCIe port interface, having the following mandatory properties:
37
38Required properties:
39- device_type: Must be "pci"
40- reg: Only the first four bytes are used to refer to the correct bus number
41  and device number.
42- #address-cells: Must be 3
43- #size-cells: Must be 2
44- #interrupt-cells: Must be 1
45- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
46  Please refer to the standard PCI bus binding document for a more detailed
47  explanation.
48- ranges: Sub-ranges distributed from the PCIe controller node. An empty
49  property is sufficient.
50
51Examples for MT7623:
52
53	hifsys: syscon@1a000000 {
54		compatible = "mediatek,mt7623-hifsys",
55			     "syscon";
56		reg = <0x1a000000 0x1000>;
57		#clock-cells = <1>;
58		#reset-cells = <1>;
59	};
60
61	pcie: pcie@1a140000 {
62		compatible = "mediatek,mt7623-pcie";
63		device_type = "pci";
64		reg = <0x1a140000 0x1000>, /* PCIe shared registers */
65		      <0x1a142000 0x1000>, /* Port0 registers */
66		      <0x1a143000 0x1000>, /* Port1 registers */
67		      <0x1a144000 0x1000>; /* Port2 registers */
68		reg-names = "subsys", "port0", "port1", "port2";
69		#address-cells = <3>;
70		#size-cells = <2>;
71		#interrupt-cells = <1>;
72		interrupt-map-mask = <0xf800 0 0 0>;
73		interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
74				<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
75				<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
76		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
77			 <&hifsys CLK_HIFSYS_PCIE0>,
78			 <&hifsys CLK_HIFSYS_PCIE1>,
79			 <&hifsys CLK_HIFSYS_PCIE2>;
80		clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
81		resets = <&hifsys HIFSYS_PCIE0_RST>,
82			 <&hifsys HIFSYS_PCIE1_RST>,
83			 <&hifsys HIFSYS_PCIE2_RST>;
84		reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
85		phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
86		       <&pcie2_phy PHY_TYPE_PCIE>;
87		phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
88		power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
89		bus-range = <0x00 0xff>;
90		ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000	/* I/O space */
91			  0x83000000 0 0x60000000 0x60000000 0 0x10000000>;	/* memory space */
92
93		pcie@0,0 {
94			reg = <0x0000 0 0 0 0>;
95			#address-cells = <3>;
96			#size-cells = <2>;
97			#interrupt-cells = <1>;
98			interrupt-map-mask = <0 0 0 0>;
99			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
100			ranges;
101		};
102
103		pcie@1,0 {
104			reg = <0x0800 0 0 0 0>;
105			#address-cells = <3>;
106			#size-cells = <2>;
107			#interrupt-cells = <1>;
108			interrupt-map-mask = <0 0 0 0>;
109			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
110			ranges;
111		};
112
113		pcie@2,0 {
114			reg = <0x1000 0 0 0 0>;
115			#address-cells = <3>;
116			#size-cells = <2>;
117			#interrupt-cells = <1>;
118			interrupt-map-mask = <0 0 0 0>;
119			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
120			ranges;
121		};
122	};
123