1* STM32 GPIO and Pin Mux/Config controller
2
3STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
4controller. It controls the input/output settings on the available pins and
5also provides ability to multiplex and configure the output of various on-chip
6controllers onto these pads.
7
8Pin controller node:
9Required properies:
10 - compatible: value should be one of the following:
11   "st,stm32f429-pinctrl"
12   "st,stm32f469-pinctrl"
13   "st,stm32f746-pinctrl"
14   "st,stm32f769-pinctrl"
15   "st,stm32h743-pinctrl"
16   "st,stm32mp157-pinctrl"
17   "st,stm32mp157-z-pinctrl"
18 - #address-cells: The value of this property must be 1
19 - #size-cells	: The value of this property must be 1
20 - ranges	: defines mapping between pin controller node (parent) to
21   gpio-bank node (children).
22 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
23   specify pins.
24
25GPIO controller/bank node:
26Required properties:
27 - gpio-controller : Indicates this device is a GPIO controller
28 - #gpio-cells	  : Should be two.
29			The first cell is the pin number
30			The second one is the polarity:
31				- 0 for active high
32				- 1 for active low
33 - reg		  : The gpio address range, relative to the pinctrl range
34 - clocks	  : clock that drives this bank
35 - st,bank-name	  : Should be a name string for this bank as specified in
36   the datasheet
37
38Optional properties:
39 - reset:	  : Reference to the reset controller
40 - st,syscfg: Should be phandle/offset/mask.
41	-The phandle to the syscon node which includes IRQ mux selection register.
42	-The offset of the IRQ mux selection register
43	-The field mask of IRQ mux, needed if different of 0xf.
44 - gpio-ranges: Define a dedicated mapping between a pin-controller and
45   a gpio controller. Format is <&phandle a b c> with:
46	-(phandle): phandle of pin-controller.
47	-(a): gpio base offset in range.
48	-(b): pin base offset in range.
49	-(c): gpio count in range
50   This entry has to be used either if there are holes inside a bank:
51	GPIOB0/B1/B2/B14/B15 (see example 2)
52   or if banks are not contiguous:
53	GPIOA/B/C/E...
54   NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller
55   have to use a "gpio-ranges" entry.
56   More details in Documentation/devicetree/bindings/gpio/gpio.txt.
57 - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line
58   used to select GPIOs as interrupts).
59 - hwlocks: reference to a phandle of a hardware spinlock provider node.
60 - st,package: Indicates the SOC package used.
61   More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
62
63Example 1:
64#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
65...
66
67	pin-controller {
68		#address-cells = <1>;
69		#size-cells = <1>;
70		compatible = "st,stm32f429-pinctrl";
71		ranges = <0 0x40020000 0x3000>;
72		pins-are-numbered;
73
74		gpioa: gpio@40020000 {
75			gpio-controller;
76			#gpio-cells = <2>;
77			reg = <0x0 0x400>;
78			resets = <&reset_ahb1 0>;
79			st,bank-name = "GPIOA";
80		};
81		...
82		pin-functions nodes follow...
83	};
84
85Example 2:
86#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
87...
88
89	pinctrl: pin-controller {
90		#address-cells = <1>;
91		#size-cells = <1>;
92		compatible = "st,stm32f429-pinctrl";
93		ranges = <0 0x40020000 0x3000>;
94		pins-are-numbered;
95
96		gpioa: gpio@40020000 {
97			gpio-controller;
98			#gpio-cells = <2>;
99			reg = <0x0 0x400>;
100			resets = <&reset_ahb1 0>;
101			st,bank-name = "GPIOA";
102			gpio-ranges = <&pinctrl 0 0 16>;
103		};
104
105		gpiob: gpio@40020400 {
106			gpio-controller;
107			#gpio-cells = <2>;
108			reg = <0x0 0x400>;
109			resets = <&reset_ahb1 0>;
110			st,bank-name = "GPIOB";
111			ngpios = 4;
112			gpio-ranges = <&pinctrl 0 16 3>,
113				      <&pinctrl 14 30 2>;
114		};
115
116
117		...
118		pin-functions nodes follow...
119	};
120
121
122Contents of function subnode node:
123----------------------------------
124Subnode format
125A pinctrl node should contain at least one subnode representing the
126pinctrl group available on the machine. Each subnode will list the
127pins it needs, and how they should be configured, with regard to muxer
128configuration, pullups, drive, output high/low and output speed.
129
130    node {
131	pinmux = <PIN_NUMBER_PINMUX>;
132	GENERIC_PINCONFIG;
133    };
134
135Required properties:
136- pinmux: integer array, represents gpio pin number and mux setting.
137  Supported pin number and mux varies for different SoCs, and are defined in
138  dt-bindings/pinctrl/<soc>-pinfunc.h directly.
139  These defines are calculated as:
140    ((port * 16 + line) << 8) | function
141  With:
142    - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
143    - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
144    - function: The function number, can be:
145      * 0 : GPIO
146      * 1 : Alternate Function 0
147      * 2 : Alternate Function 1
148      * 3 : Alternate Function 2
149      * ...
150      * 16 : Alternate Function 15
151      * 17 : Analog
152
153  To simplify the usage, macro is available to generate "pinmux" field.
154  This macro is available here:
155    - include/dt-bindings/pinctrl/stm32-pinfunc.h
156
157  Some examples of using macro:
158    /* GPIO A9 set as alernate function 2 */
159    ... {
160		pinmux = <STM32_PINMUX('A', 9, AF2)>;
161    };
162    /* GPIO A9 set as GPIO  */
163    ... {
164		pinmux = <STM32_PINMUX('A', 9, GPIO)>;
165    };
166    /* GPIO A9 set as analog */
167    ... {
168		pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
169    };
170
171Optional properties:
172- GENERIC_PINCONFIG: is the generic pinconfig options to use.
173  Available options are:
174   - bias-disable,
175   - bias-pull-down,
176   - bias-pull-up,
177   - drive-push-pull,
178   - drive-open-drain,
179   - output-low
180   - output-high
181   - slew-rate = <x>, with x being:
182       < 0 > : Low speed
183       < 1 > : Medium speed
184       < 2 > : Fast speed
185       < 3 > : High speed
186
187Example:
188
189pin-controller {
190...
191	usart1_pins_a: usart1@0 {
192		pins1 {
193			pinmux = <STM32_PINMUX('A', 9, AF7)>;
194			bias-disable;
195			drive-push-pull;
196			slew-rate = <0>;
197		};
198		pins2 {
199			pinmux = <STM32_PINMUX('A', 10, AF7)>;
200			bias-disable;
201		};
202	};
203};
204
205&usart1 {
206	pinctrl-0 = <&usart1_pins_a>;
207	pinctrl-names = "default";
208};
209