1Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface 2and Synopsys DesignWare High Performance Synchronous Serial Interface 3 4Required properties: 5- compatible : One of 6 "altr,socfpga-spi", 7 "altr,socfpga-arria10-spi", 8 "canaan,kendryte-k210-spi", 9 "canaan,kendryte-k210-ssi", 10 "intel,stratix10-spi", 11 "intel,agilex-spi", 12 "mscc,ocelot-spi", 13 or "mscc,jaguar2-spi"; 14 and one of 15 "snps,dw-apb-ssi-3.20a", 16 "snps,dw-apb-ssi-3.22a", 17 "snps,dw-apb-ssi-3.23", 18 "snps,dw-apb-ssi-4.00a", 19 "snps,dw-apb-ssi-4.01", 20 or "snps,dwc-ssi-1.01a". 21 "snps,dw-apb-ssi" may also be used, but is deprecated in favor of specific 22 version strings. 23- reg : The register base for the controller. For "mscc,<soc>-spi", a second 24 register set is required (named ICPU_CFG:SPI_MST) 25- #address-cells : <1>, as required by generic SPI binding. 26- #size-cells : <0>, also as required by generic SPI binding. 27- clocks : phandles for the clocks, see the description of clock-names below. 28 The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock 29 is optional. If a single clock is specified but no clock-name, it is the 30 "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first. 31 32Optional properties: 33- clock-names : Contains the names of the clocks: 34 "ssi_clk", for the core clock used to generate the external SPI clock. 35 "pclk", the interface clock, required for register access. 36- cs-gpios : Specifies the gpio pins to be used for chipselects. 37- num-cs : The number of chipselects. If omitted, this will default to 4. 38- reg-io-width : The I/O register width (in bytes) implemented by this 39 device. Supported values are 2 or 4 (the default). 40 41Child nodes as per the generic SPI binding. 42 43Example: 44 45 spi@fff00000 { 46 compatible = "altr,socfpga-arria10-spi", 47 "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; 48 reg = <0xfff00000 0x1000>; 49 interrupts = <0 154 4>; 50 #address-cells = <1>; 51 #size-cells = <0>; 52 clocks = <&spi_m_clk>; 53 num-cs = <2>; 54 cs-gpios = <&gpio0 13 0>, 55 <&gpio0 14 0>; 56 }; 57