1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Common clock driver for Actions Semi SoCs.
4 *
5 * Copyright (C) 2015 Actions Semi Co., Ltd.
6 * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include "clk_owl.h"
12 #include <asm/io.h>
13 #if defined(CONFIG_MACH_S900)
14 #include <asm/arch-owl/regs_s900.h>
15 #include <dt-bindings/clock/actions,s900-cmu.h>
16 #elif defined(CONFIG_MACH_S700)
17 #include <asm/arch-owl/regs_s700.h>
18 #include <dt-bindings/clock/actions,s700-cmu.h>
19 #endif
20 #include <linux/bitops.h>
21 #include <linux/delay.h>
22
owl_clk_init(struct owl_clk_priv * priv)23 void owl_clk_init(struct owl_clk_priv *priv)
24 {
25 u32 bus_clk = 0, core_pll, dev_pll;
26
27 #if defined(CONFIG_MACH_S900)
28 /* Enable ASSIST_PLL */
29 setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
30 udelay(PLL_STABILITY_WAIT_US);
31 #endif
32
33 /* Source HOSC to DEV_CLK */
34 clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
35
36 /* Configure BUS_CLK */
37 bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |
38 CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
39 CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
40 writel(bus_clk, priv->base + CMU_BUSCLK);
41
42 udelay(PLL_STABILITY_WAIT_US);
43
44 /* Configure CORE_PLL */
45 core_pll = readl(priv->base + CMU_COREPLL);
46 core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
47 writel(core_pll, priv->base + CMU_COREPLL);
48
49 udelay(PLL_STABILITY_WAIT_US);
50
51 /* Configure DEV_PLL */
52 dev_pll = readl(priv->base + CMU_DEVPLL);
53 dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
54 writel(dev_pll, priv->base + CMU_DEVPLL);
55
56 udelay(PLL_STABILITY_WAIT_US);
57
58 /* Source CORE_PLL for CORE_CLK */
59 clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,
60 CMU_CORECLK_CPLL);
61
62 /* Source DEV_PLL for DEV_CLK */
63 setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
64
65 udelay(PLL_STABILITY_WAIT_US);
66 }
67
owl_clk_enable(struct clk * clk)68 int owl_clk_enable(struct clk *clk)
69 {
70 struct owl_clk_priv *priv = dev_get_priv(clk->dev);
71 enum owl_soc model = dev_get_driver_data(clk->dev);
72
73 switch (clk->id) {
74 case CLK_UART5:
75 if (model != S900)
76 return -EINVAL;
77 /* Source HOSC for UART5 interface */
78 clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
79 /* Enable UART5 interface clock */
80 setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
81 break;
82 case CLK_UART3:
83 if (model != S700)
84 return -EINVAL;
85 /* Source HOSC for UART3 interface */
86 clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL);
87 /* Enable UART3 interface clock */
88 setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
89 break;
90 case CLK_RMII_REF:
91 case CLK_ETHERNET:
92 setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH);
93 setbits_le32(priv->base + CMU_ETHERNETPLL, 5);
94 break;
95 default:
96 return -EINVAL;
97 }
98
99 return 0;
100 }
101
owl_clk_disable(struct clk * clk)102 int owl_clk_disable(struct clk *clk)
103 {
104 struct owl_clk_priv *priv = dev_get_priv(clk->dev);
105 enum owl_soc model = dev_get_driver_data(clk->dev);
106
107 switch (clk->id) {
108 case CLK_UART5:
109 if (model != S900)
110 return -EINVAL;
111 /* Disable UART5 interface clock */
112 clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
113 break;
114 case CLK_UART3:
115 if (model != S700)
116 return -EINVAL;
117 /* Disable UART3 interface clock */
118 clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
119 break;
120 case CLK_RMII_REF:
121 case CLK_ETHERNET:
122 clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH);
123 break;
124 default:
125 return -EINVAL;
126 }
127
128 return 0;
129 }
130
owl_clk_probe(struct udevice * dev)131 static int owl_clk_probe(struct udevice *dev)
132 {
133 struct owl_clk_priv *priv = dev_get_priv(dev);
134
135 priv->base = dev_read_addr(dev);
136 if (priv->base == FDT_ADDR_T_NONE)
137 return -EINVAL;
138
139 /* setup necessary clocks */
140 owl_clk_init(priv);
141
142 return 0;
143 }
144
145 static const struct clk_ops owl_clk_ops = {
146 .enable = owl_clk_enable,
147 .disable = owl_clk_disable,
148 };
149
150 static const struct udevice_id owl_clk_ids[] = {
151 #if defined(CONFIG_MACH_S900)
152 { .compatible = "actions,s900-cmu", .data = S900 },
153 #elif defined(CONFIG_MACH_S700)
154 { .compatible = "actions,s700-cmu", .data = S700 },
155 #endif
156 { }
157 };
158
159 U_BOOT_DRIVER(clk_owl) = {
160 .name = "clk_owl",
161 .id = UCLASS_CLK,
162 .of_match = owl_clk_ids,
163 .ops = &owl_clk_ops,
164 .priv_auto = sizeof(struct owl_clk_priv),
165 .probe = owl_clk_probe,
166 };
167