1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Renesas RCar Gen2 CPG MSSR driver
4 *
5 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
6 *
7 * Based on the following driver from Linux kernel:
8 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9 *
10 * Copyright (C) 2016 Glider bvba
11 */
12
13 #include <common.h>
14 #include <clk-uclass.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <log.h>
18 #include <asm/global_data.h>
19 #include <asm/io.h>
20
21 #include <dt-bindings/clock/renesas-cpg-mssr.h>
22
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen2-cpg.h"
25
26 #define CPG_RST_MODEMR 0x0060
27
28 #define CPG_PLL0CR 0x00d8
29 #define CPG_SDCKCR 0x0074
30
31 struct clk_div_table {
32 u8 val;
33 u8 div;
34 };
35
36 /* SDHI divisors */
37 static const struct clk_div_table cpg_sdh_div_table[] = {
38 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
39 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
40 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
41 };
42
43 static const struct clk_div_table cpg_sd01_div_table[] = {
44 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
45 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
46 { 0, 0 },
47 };
48
gen2_clk_get_sdh_div(const struct clk_div_table * table,u8 val)49 static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 val)
50 {
51 for (;;) {
52 if (!(*table).div)
53 return 0xff;
54
55 if ((*table).val == val)
56 return (*table).div;
57
58 table++;
59 }
60 }
61
gen2_clk_enable(struct clk * clk)62 static int gen2_clk_enable(struct clk *clk)
63 {
64 struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
65
66 return renesas_clk_endisable(clk, priv->base, true);
67 }
68
gen2_clk_disable(struct clk * clk)69 static int gen2_clk_disable(struct clk *clk)
70 {
71 struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
72
73 return renesas_clk_endisable(clk, priv->base, false);
74 }
75
gen2_clk_get_rate(struct clk * clk)76 static ulong gen2_clk_get_rate(struct clk *clk)
77 {
78 struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
79 struct cpg_mssr_info *info = priv->info;
80 struct clk parent;
81 const struct cpg_core_clk *core;
82 const struct rcar_gen2_cpg_pll_config *pll_config =
83 priv->cpg_pll_config;
84 u32 value, mult, div, rate = 0;
85 int ret;
86
87 debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
88
89 ret = renesas_clk_get_parent(clk, info, &parent);
90 if (ret) {
91 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
92 return ret;
93 }
94
95 if (renesas_clk_is_mod(clk)) {
96 rate = gen2_clk_get_rate(&parent);
97 debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
98 __func__, __LINE__, parent.id, rate);
99 return rate;
100 }
101
102 ret = renesas_clk_get_core(clk, info, &core);
103 if (ret)
104 return ret;
105
106 switch (core->type) {
107 case CLK_TYPE_IN:
108 if (core->id == info->clk_extal_id) {
109 rate = clk_get_rate(&priv->clk_extal);
110 debug("%s[%i] EXTAL clk: rate=%u\n",
111 __func__, __LINE__, rate);
112 return rate;
113 }
114
115 if (core->id == info->clk_extal_usb_id) {
116 rate = clk_get_rate(&priv->clk_extal_usb);
117 debug("%s[%i] EXTALR clk: rate=%u\n",
118 __func__, __LINE__, rate);
119 return rate;
120 }
121
122 return -EINVAL;
123
124 case CLK_TYPE_FF:
125 rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
126 debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
127 __func__, __LINE__,
128 core->parent, core->mult, core->div, rate);
129 return rate;
130
131 case CLK_TYPE_DIV6P1: /* DIV6 Clock with 1 parent clock */
132 value = (readl(priv->base + core->offset) & 0x3f) + 1;
133 rate = gen2_clk_get_rate(&parent) / value;
134 debug("%s[%i] DIV6P1 clk: parent=%i div=%i => rate=%u\n",
135 __func__, __LINE__,
136 core->parent, value, rate);
137 return rate;
138
139 case CLK_TYPE_GEN2_MAIN:
140 rate = gen2_clk_get_rate(&parent) / pll_config->extal_div;
141 debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
142 __func__, __LINE__,
143 core->parent, pll_config->extal_div, rate);
144 return rate;
145
146 case CLK_TYPE_GEN2_PLL0:
147 /*
148 * PLL0 is a configurable multiplier clock except on R-Car
149 * V2H/E2. Register the PLL0 clock as a fixed factor clock for
150 * now as there's no generic multiplier clock implementation and
151 * we currently have no need to change the multiplier value.
152 */
153 mult = pll_config->pll0_mult;
154 if (!mult) {
155 value = readl(priv->base + CPG_PLL0CR);
156 mult = (((value >> 24) & 0x7f) + 1) * 2;
157 }
158
159 rate = (gen2_clk_get_rate(&parent) * mult) / info->pll0_div;
160 debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
161 __func__, __LINE__, core->parent, mult, rate);
162 return rate;
163
164 case CLK_TYPE_GEN2_PLL1:
165 rate = (gen2_clk_get_rate(&parent) * pll_config->pll1_mult) / 2;
166 debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
167 __func__, __LINE__,
168 core->parent, pll_config->pll1_mult, rate);
169 return rate;
170
171 case CLK_TYPE_GEN2_PLL3:
172 rate = gen2_clk_get_rate(&parent) * pll_config->pll3_mult;
173 debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
174 __func__, __LINE__,
175 core->parent, pll_config->pll3_mult, rate);
176 return rate;
177
178 case CLK_TYPE_GEN2_SDH:
179 value = (readl(priv->base + CPG_SDCKCR) >> 8) & 0xf;
180 div = gen2_clk_get_sdh_div(cpg_sdh_div_table, value);
181 rate = gen2_clk_get_rate(&parent) / div;
182 debug("%s[%i] SDH clk: parent=%i div=%i => rate=%u\n",
183 __func__, __LINE__,
184 core->parent, div, rate);
185 return rate;
186
187 case CLK_TYPE_GEN2_SD0:
188 value = (readl(priv->base + CPG_SDCKCR) >> 4) & 0xf;
189 div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
190 rate = gen2_clk_get_rate(&parent) / div;
191 debug("%s[%i] SD0 clk: parent=%i div=%i => rate=%u\n",
192 __func__, __LINE__,
193 core->parent, div, rate);
194 return rate;
195
196 case CLK_TYPE_GEN2_SD1:
197 value = (readl(priv->base + CPG_SDCKCR) >> 0) & 0xf;
198 div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
199 rate = gen2_clk_get_rate(&parent) / div;
200 debug("%s[%i] SD1 clk: parent=%i div=%i => rate=%u\n",
201 __func__, __LINE__,
202 core->parent, div, rate);
203 return rate;
204 }
205
206 printf("%s[%i] unknown fail\n", __func__, __LINE__);
207
208 return -ENOENT;
209 }
210
gen2_clk_setup_mmcif_div(struct clk * clk,ulong rate)211 static int gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate)
212 {
213 struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
214 struct cpg_mssr_info *info = priv->info;
215 const struct cpg_core_clk *core;
216 struct clk parent, pparent;
217 u32 val;
218 int ret;
219
220 ret = renesas_clk_get_parent(clk, info, &parent);
221 if (ret) {
222 debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
223 return ret;
224 }
225
226 if (renesas_clk_is_mod(&parent))
227 return 0;
228
229 ret = renesas_clk_get_core(&parent, info, &core);
230 if (ret)
231 return ret;
232
233 if (strcmp(core->name, "mmc0") && strcmp(core->name, "mmc1"))
234 return 0;
235
236 ret = renesas_clk_get_parent(&parent, info, &pparent);
237 if (ret) {
238 debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
239 return ret;
240 }
241
242 val = (gen2_clk_get_rate(&pparent) / rate) - 1;
243
244 debug("%s[%i] MMCIF offset=%x\n", __func__, __LINE__, core->offset);
245
246 writel(val, priv->base + core->offset);
247
248 return 0;
249 }
250
gen2_clk_set_rate(struct clk * clk,ulong rate)251 static ulong gen2_clk_set_rate(struct clk *clk, ulong rate)
252 {
253 /* Force correct MMC-IF divider configuration if applicable */
254 gen2_clk_setup_mmcif_div(clk, rate);
255 return gen2_clk_get_rate(clk);
256 }
257
gen2_clk_of_xlate(struct clk * clk,struct ofnode_phandle_args * args)258 static int gen2_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
259 {
260 if (args->args_count != 2) {
261 debug("Invaild args_count: %d\n", args->args_count);
262 return -EINVAL;
263 }
264
265 clk->id = (args->args[0] << 16) | args->args[1];
266
267 return 0;
268 }
269
270 const struct clk_ops gen2_clk_ops = {
271 .enable = gen2_clk_enable,
272 .disable = gen2_clk_disable,
273 .get_rate = gen2_clk_get_rate,
274 .set_rate = gen2_clk_set_rate,
275 .of_xlate = gen2_clk_of_xlate,
276 };
277
gen2_clk_probe(struct udevice * dev)278 int gen2_clk_probe(struct udevice *dev)
279 {
280 struct gen2_clk_priv *priv = dev_get_priv(dev);
281 struct cpg_mssr_info *info =
282 (struct cpg_mssr_info *)dev_get_driver_data(dev);
283 fdt_addr_t rst_base;
284 u32 cpg_mode;
285 int ret;
286
287 priv->base = dev_read_addr_ptr(dev);
288 if (!priv->base)
289 return -EINVAL;
290
291 priv->info = info;
292 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
293 if (ret < 0)
294 return ret;
295
296 rst_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, ret, "reg",
297 0, NULL, false);
298 if (rst_base == FDT_ADDR_T_NONE)
299 return -EINVAL;
300
301 cpg_mode = readl(rst_base + CPG_RST_MODEMR);
302
303 priv->cpg_pll_config =
304 (struct rcar_gen2_cpg_pll_config *)info->get_pll_config(cpg_mode);
305 if (!priv->cpg_pll_config->extal_div)
306 return -EINVAL;
307
308 ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
309 if (ret < 0)
310 return ret;
311
312 if (info->extal_usb_node) {
313 ret = clk_get_by_name(dev, info->extal_usb_node,
314 &priv->clk_extal_usb);
315 if (ret < 0)
316 return ret;
317 }
318
319 return 0;
320 }
321
gen2_clk_remove(struct udevice * dev)322 int gen2_clk_remove(struct udevice *dev)
323 {
324 struct gen2_clk_priv *priv = dev_get_priv(dev);
325
326 return renesas_clk_remove(priv->base, priv->info);
327 }
328