1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * (C) Copyright 2015 Google, Inc
4 */
5
6 #include <common.h>
7 #include <clk-uclass.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <log.h>
11 #include <malloc.h>
12 #include <syscon.h>
13 #include <asm/io.h>
14 #include <asm/arch-rockchip/clock.h>
15 #include <asm/arch-rockchip/cru_rk3036.h>
16 #include <asm/arch-rockchip/hardware.h>
17 #include <dm/device-internal.h>
18 #include <dm/lists.h>
19 #include <dt-bindings/clock/rk3036-cru.h>
20 #include <linux/delay.h>
21 #include <linux/log2.h>
22 #include <linux/stringify.h>
23
24 enum {
25 VCO_MAX_HZ = 2400U * 1000000,
26 VCO_MIN_HZ = 600 * 1000000,
27 OUTPUT_MAX_HZ = 2400U * 1000000,
28 OUTPUT_MIN_HZ = 24 * 1000000,
29 };
30
31 #define RATE_TO_DIV(input_rate, output_rate) \
32 ((input_rate) / (output_rate) - 1);
33
34 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
35
36 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
37 .refdiv = _refdiv,\
38 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
39 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
40 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
41 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
42 #hz "Hz cannot be hit with PLL "\
43 "divisors on line " __stringify(__LINE__));
44
45 /* use integer mode*/
46 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
47 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
48
rkclk_set_pll(struct rk3036_cru * cru,enum rk_clk_id clk_id,const struct pll_div * div)49 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
50 const struct pll_div *div)
51 {
52 int pll_id = rk_pll_id(clk_id);
53 struct rk3036_pll *pll = &cru->pll[pll_id];
54
55 /* All PLLs have same VCO and output frequency range restrictions. */
56 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
57 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
58
59 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\
60 vco=%u Hz, output=%u Hz\n",
61 pll, div->fbdiv, div->refdiv, div->postdiv1,
62 div->postdiv2, vco_hz, output_hz);
63 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
64 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
65
66 /* use integer mode */
67 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
68
69 rk_clrsetreg(&pll->con0,
70 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
71 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
72 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
73 (div->postdiv2 << PLL_POSTDIV2_SHIFT |
74 div->refdiv << PLL_REFDIV_SHIFT));
75
76 /* waiting for pll lock */
77 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
78 udelay(1);
79
80 return 0;
81 }
82
rkclk_init(struct rk3036_cru * cru)83 static void rkclk_init(struct rk3036_cru *cru)
84 {
85 u32 aclk_div;
86 u32 hclk_div;
87 u32 pclk_div;
88
89 /* pll enter slow-mode */
90 rk_clrsetreg(&cru->cru_mode_con,
91 GPLL_MODE_MASK | APLL_MODE_MASK,
92 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
93 APLL_MODE_SLOW << APLL_MODE_SHIFT);
94
95 /* init pll */
96 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
97 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
98
99 /*
100 * select apll as cpu/core clock pll source and
101 * set up dependent divisors for PERI and ACLK clocks.
102 * core hz : apll = 1:1
103 */
104 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
105 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
106
107 pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
108 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
109
110 rk_clrsetreg(&cru->cru_clksel_con[0],
111 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
112 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
113 0 << CORE_DIV_CON_SHIFT);
114
115 rk_clrsetreg(&cru->cru_clksel_con[1],
116 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
117 aclk_div << CORE_ACLK_DIV_SHIFT |
118 pclk_div << CORE_PERI_DIV_SHIFT);
119
120 /*
121 * select apll as pd_bus bus clock source and
122 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
123 */
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
126
127 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
128 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
129
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
132
133 rk_clrsetreg(&cru->cru_clksel_con[0],
134 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
135 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
136 aclk_div << BUS_ACLK_DIV_SHIFT);
137
138 rk_clrsetreg(&cru->cru_clksel_con[1],
139 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
140 pclk_div << BUS_PCLK_DIV_SHIFT |
141 hclk_div << BUS_HCLK_DIV_SHIFT);
142
143 /*
144 * select gpll as pd_peri bus clock source and
145 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
146 */
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
149
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
151 assert((1 << hclk_div) * PERI_HCLK_HZ ==
152 PERI_ACLK_HZ && (hclk_div < 0x4));
153
154 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
155 assert((1 << pclk_div) * PERI_PCLK_HZ ==
156 PERI_ACLK_HZ && pclk_div < 0x8);
157
158 rk_clrsetreg(&cru->cru_clksel_con[10],
159 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
160 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
161 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
162 pclk_div << PERI_PCLK_DIV_SHIFT |
163 hclk_div << PERI_HCLK_DIV_SHIFT |
164 aclk_div << PERI_ACLK_DIV_SHIFT);
165
166 /* PLL enter normal-mode */
167 rk_clrsetreg(&cru->cru_mode_con,
168 GPLL_MODE_MASK | APLL_MODE_MASK,
169 GPLL_MODE_NORM << GPLL_MODE_SHIFT |
170 APLL_MODE_NORM << APLL_MODE_SHIFT);
171 }
172
173 /* Get pll rate by id */
rkclk_pll_get_rate(struct rk3036_cru * cru,enum rk_clk_id clk_id)174 static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
175 enum rk_clk_id clk_id)
176 {
177 uint32_t refdiv, fbdiv, postdiv1, postdiv2;
178 uint32_t con;
179 int pll_id = rk_pll_id(clk_id);
180 struct rk3036_pll *pll = &cru->pll[pll_id];
181 static u8 clk_shift[CLK_COUNT] = {
182 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
183 GPLL_MODE_SHIFT, 0xff
184 };
185 static u32 clk_mask[CLK_COUNT] = {
186 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff,
187 GPLL_MODE_MASK, 0xffffffff
188 };
189 uint shift;
190 uint mask;
191
192 con = readl(&cru->cru_mode_con);
193 shift = clk_shift[clk_id];
194 mask = clk_mask[clk_id];
195
196 switch ((con & mask) >> shift) {
197 case GPLL_MODE_SLOW:
198 return OSC_HZ;
199 case GPLL_MODE_NORM:
200
201 /* normal mode */
202 con = readl(&pll->con0);
203 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
204 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
205 con = readl(&pll->con1);
206 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
207 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
208 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
209 case GPLL_MODE_DEEP:
210 default:
211 return 32768;
212 }
213 }
214
rockchip_mmc_get_clk(struct rk3036_cru * cru,uint clk_general_rate,int periph)215 static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
216 int periph)
217 {
218 uint src_rate;
219 uint div, mux;
220 u32 con;
221
222 switch (periph) {
223 case HCLK_EMMC:
224 case SCLK_EMMC:
225 con = readl(&cru->cru_clksel_con[12]);
226 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
227 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
228 break;
229 case HCLK_SDIO:
230 case SCLK_SDIO:
231 con = readl(&cru->cru_clksel_con[12]);
232 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
233 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
234 break;
235 default:
236 return -EINVAL;
237 }
238
239 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
240 return DIV_TO_RATE(src_rate, div) / 2;
241 }
242
rockchip_mmc_set_clk(struct rk3036_cru * cru,uint clk_general_rate,int periph,uint freq)243 static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
244 int periph, uint freq)
245 {
246 int src_clk_div;
247 int mux;
248
249 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
250
251 /* mmc clock auto divide 2 in internal */
252 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
253
254 if (src_clk_div > 128) {
255 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
256 assert(src_clk_div - 1 < 128);
257 mux = EMMC_SEL_24M;
258 } else {
259 mux = EMMC_SEL_GPLL;
260 }
261
262 switch (periph) {
263 case HCLK_EMMC:
264 case SCLK_EMMC:
265 rk_clrsetreg(&cru->cru_clksel_con[12],
266 EMMC_PLL_MASK | EMMC_DIV_MASK,
267 mux << EMMC_PLL_SHIFT |
268 (src_clk_div - 1) << EMMC_DIV_SHIFT);
269 break;
270 case HCLK_SDIO:
271 case SCLK_SDIO:
272 rk_clrsetreg(&cru->cru_clksel_con[11],
273 MMC0_PLL_MASK | MMC0_DIV_MASK,
274 mux << MMC0_PLL_SHIFT |
275 (src_clk_div - 1) << MMC0_DIV_SHIFT);
276 break;
277 default:
278 return -EINVAL;
279 }
280
281 return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
282 }
283
rk3036_clk_get_rate(struct clk * clk)284 static ulong rk3036_clk_get_rate(struct clk *clk)
285 {
286 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
287
288 switch (clk->id) {
289 case 0 ... 63:
290 return rkclk_pll_get_rate(priv->cru, clk->id);
291 default:
292 return -ENOENT;
293 }
294 }
295
rk3036_clk_set_rate(struct clk * clk,ulong rate)296 static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)
297 {
298 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
299 ulong new_rate, gclk_rate;
300
301 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
302 switch (clk->id) {
303 case 0 ... 63:
304 return 0;
305 case HCLK_EMMC:
306 case SCLK_EMMC:
307 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
308 clk->id, rate);
309 break;
310 default:
311 return -ENOENT;
312 }
313
314 return new_rate;
315 }
316
317 static struct clk_ops rk3036_clk_ops = {
318 .get_rate = rk3036_clk_get_rate,
319 .set_rate = rk3036_clk_set_rate,
320 };
321
rk3036_clk_of_to_plat(struct udevice * dev)322 static int rk3036_clk_of_to_plat(struct udevice *dev)
323 {
324 struct rk3036_clk_priv *priv = dev_get_priv(dev);
325
326 priv->cru = dev_read_addr_ptr(dev);
327
328 return 0;
329 }
330
rk3036_clk_probe(struct udevice * dev)331 static int rk3036_clk_probe(struct udevice *dev)
332 {
333 struct rk3036_clk_priv *priv = dev_get_priv(dev);
334
335 rkclk_init(priv->cru);
336
337 return 0;
338 }
339
rk3036_clk_bind(struct udevice * dev)340 static int rk3036_clk_bind(struct udevice *dev)
341 {
342 int ret;
343 struct udevice *sys_child;
344 struct sysreset_reg *priv;
345
346 /* The reset driver does not have a device node, so bind it here */
347 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
348 &sys_child);
349 if (ret) {
350 debug("Warning: No sysreset driver: ret=%d\n", ret);
351 } else {
352 priv = malloc(sizeof(struct sysreset_reg));
353 priv->glb_srst_fst_value = offsetof(struct rk3036_cru,
354 cru_glb_srst_fst_value);
355 priv->glb_srst_snd_value = offsetof(struct rk3036_cru,
356 cru_glb_srst_snd_value);
357 dev_set_priv(sys_child, priv);
358 }
359
360 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
361 ret = offsetof(struct rk3036_cru, cru_softrst_con[0]);
362 ret = rockchip_reset_bind(dev, ret, 9);
363 if (ret)
364 debug("Warning: software reset driver bind faile\n");
365 #endif
366
367 return 0;
368 }
369
370 static const struct udevice_id rk3036_clk_ids[] = {
371 { .compatible = "rockchip,rk3036-cru" },
372 { }
373 };
374
375 U_BOOT_DRIVER(rockchip_rk3036_cru) = {
376 .name = "clk_rk3036",
377 .id = UCLASS_CLK,
378 .of_match = rk3036_clk_ids,
379 .priv_auto = sizeof(struct rk3036_clk_priv),
380 .of_to_plat = rk3036_clk_of_to_plat,
381 .ops = &rk3036_clk_ops,
382 .bind = rk3036_clk_bind,
383 .probe = rk3036_clk_probe,
384 };
385