1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
4 */
5
6 #include <common.h>
7 #include <clk-uclass.h>
8 #include <dm.h>
9 #include <log.h>
10 #include <malloc.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch-tegra/clk_rst.h>
13
tegra_car_clk_request(struct clk * clk)14 static int tegra_car_clk_request(struct clk *clk)
15 {
16 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
17 clk->id);
18
19 /*
20 * Note that the first PERIPH_ID_COUNT clock IDs (where the value
21 * varies per SoC) are the peripheral clocks, which use a numbering
22 * scheme that matches HW registers 1:1. There are other clock IDs
23 * beyond this that are assigned arbitrarily by the Tegra CAR DT
24 * binding. Due to the implementation of this driver, it currently
25 * only supports the peripheral IDs.
26 */
27 if (clk->id >= PERIPH_ID_COUNT)
28 return -EINVAL;
29
30 return 0;
31 }
32
tegra_car_clk_free(struct clk * clk)33 static int tegra_car_clk_free(struct clk *clk)
34 {
35 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
36 clk->id);
37
38 return 0;
39 }
40
tegra_car_clk_get_rate(struct clk * clk)41 static ulong tegra_car_clk_get_rate(struct clk *clk)
42 {
43 enum clock_id parent;
44
45 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
46 clk->id);
47
48 parent = clock_get_periph_parent(clk->id);
49 return clock_get_periph_rate(clk->id, parent);
50 }
51
tegra_car_clk_set_rate(struct clk * clk,ulong rate)52 static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
53 {
54 enum clock_id parent;
55
56 debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
57 clk->dev, clk->id);
58
59 parent = clock_get_periph_parent(clk->id);
60 return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
61 }
62
tegra_car_clk_enable(struct clk * clk)63 static int tegra_car_clk_enable(struct clk *clk)
64 {
65 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
66 clk->id);
67
68 clock_enable(clk->id);
69
70 return 0;
71 }
72
tegra_car_clk_disable(struct clk * clk)73 static int tegra_car_clk_disable(struct clk *clk)
74 {
75 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
76 clk->id);
77
78 clock_disable(clk->id);
79
80 return 0;
81 }
82
83 static struct clk_ops tegra_car_clk_ops = {
84 .request = tegra_car_clk_request,
85 .rfree = tegra_car_clk_free,
86 .get_rate = tegra_car_clk_get_rate,
87 .set_rate = tegra_car_clk_set_rate,
88 .enable = tegra_car_clk_enable,
89 .disable = tegra_car_clk_disable,
90 };
91
tegra_car_clk_probe(struct udevice * dev)92 static int tegra_car_clk_probe(struct udevice *dev)
93 {
94 debug("%s(dev=%p)\n", __func__, dev);
95
96 return 0;
97 }
98
99 U_BOOT_DRIVER(tegra_car_clk) = {
100 .name = "tegra_car_clk",
101 .id = UCLASS_CLK,
102 .probe = tegra_car_clk_probe,
103 .ops = &tegra_car_clk_ops,
104 };
105