1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright Altera Corporation (C) 2014-2015
4 */
5 #include <common.h>
6 #include <dm.h>
7 #include <errno.h>
8 #include <div64.h>
9 #include <init.h>
10 #include <log.h>
11 #include <ram.h>
12 #include <reset.h>
13 #include <watchdog.h>
14 #include <asm/arch/fpga_manager.h>
15 #include <asm/arch/reset_manager.h>
16 #include <asm/arch/sdram.h>
17 #include <asm/arch/system_manager.h>
18 #include <asm/bitops.h>
19 #include <asm/io.h>
20 #include <dm/device_compat.h>
21
22 #include "sequencer.h"
23
24 #ifdef CONFIG_SPL_BUILD
25
26 struct altera_gen5_sdram_priv {
27 struct ram_info info;
28 };
29
30 struct altera_gen5_sdram_plat {
31 struct socfpga_sdr *sdr;
32 };
33
34 struct sdram_prot_rule {
35 u32 sdram_start; /* SDRAM start address */
36 u32 sdram_end; /* SDRAM end address */
37 u32 rule; /* SDRAM protection rule number: 0-19 */
38 int valid; /* Rule valid or not? 1 - valid, 0 not*/
39
40 u32 security;
41 u32 portmask;
42 u32 result;
43 u32 lo_prot_id;
44 u32 hi_prot_id;
45 };
46
47 static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
48
49 /**
50 * get_errata_rows() - Up the number of DRAM rows to cover entire address space
51 * @cfg: SDRAM controller configuration data
52 *
53 * SDRAM Failure happens when accessing non-existent memory. Artificially
54 * increase the number of rows so that the memory controller thinks it has
55 * 4GB of RAM. This function returns such amount of rows.
56 */
get_errata_rows(const struct socfpga_sdram_config * cfg)57 static int get_errata_rows(const struct socfpga_sdram_config *cfg)
58 {
59 /* Define constant for 4G memory - used for SDRAM errata workaround */
60 #define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
61 const unsigned long long memsize = MEMSIZE_4G;
62 const unsigned int cs =
63 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
64 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
65 const unsigned int rows =
66 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
67 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
68 const unsigned int banks =
69 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
70 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
71 const unsigned int cols =
72 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
73 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
74 const unsigned int width = 8;
75
76 unsigned long long newrows;
77 int bits, inewrowslog2;
78
79 debug("workaround rows - memsize %lld\n", memsize);
80 debug("workaround rows - cs %d\n", cs);
81 debug("workaround rows - width %d\n", width);
82 debug("workaround rows - rows %d\n", rows);
83 debug("workaround rows - banks %d\n", banks);
84 debug("workaround rows - cols %d\n", cols);
85
86 newrows = lldiv(memsize, cs * (width / 8));
87 debug("rows workaround - term1 %lld\n", newrows);
88
89 newrows = lldiv(newrows, (1 << banks) * (1 << cols));
90 debug("rows workaround - term2 %lld\n", newrows);
91
92 /*
93 * Compute the hamming weight - same as number of bits set.
94 * Need to see if result is ordinal power of 2 before
95 * attempting log2 of result.
96 */
97 bits = generic_hweight32(newrows);
98
99 debug("rows workaround - bits %d\n", bits);
100
101 if (bits != 1) {
102 printf("SDRAM workaround failed, bits set %d\n", bits);
103 return rows;
104 }
105
106 if (newrows > UINT_MAX) {
107 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
108 return rows;
109 }
110
111 inewrowslog2 = __ilog2(newrows);
112
113 debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
114
115 if (inewrowslog2 == -1) {
116 printf("SDRAM workaround failed, newrows %lld\n", newrows);
117 return rows;
118 }
119
120 return inewrowslog2;
121 }
122
123 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
sdram_set_rule(struct socfpga_sdr_ctrl * sdr_ctrl,struct sdram_prot_rule * prule)124 static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
125 struct sdram_prot_rule *prule)
126 {
127 u32 lo_addr_bits;
128 u32 hi_addr_bits;
129 int ruleno = prule->rule;
130
131 /* Select the rule */
132 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
133
134 /* Obtain the address bits */
135 lo_addr_bits = prule->sdram_start >> 20ULL;
136 hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
137
138 debug("sdram set rule start %x, %d\n", lo_addr_bits,
139 prule->sdram_start);
140 debug("sdram set rule end %x, %d\n", hi_addr_bits,
141 prule->sdram_end);
142
143 /* Set rule addresses */
144 writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
145
146 /* Set rule protection ids */
147 writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
148 &sdr_ctrl->prot_rule_id);
149
150 /* Set the rule data */
151 writel(prule->security | (prule->valid << 2) |
152 (prule->portmask << 3) | (prule->result << 13),
153 &sdr_ctrl->prot_rule_data);
154
155 /* write the rule */
156 writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
157
158 /* Set rule number to 0 by default */
159 writel(0, &sdr_ctrl->prot_rule_rdwr);
160 }
161
sdram_get_rule(struct socfpga_sdr_ctrl * sdr_ctrl,struct sdram_prot_rule * prule)162 static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
163 struct sdram_prot_rule *prule)
164 {
165 u32 addr;
166 u32 id;
167 u32 data;
168 int ruleno = prule->rule;
169
170 /* Read the rule */
171 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
172 writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
173
174 /* Get the addresses */
175 addr = readl(&sdr_ctrl->prot_rule_addr);
176 prule->sdram_start = (addr & 0xFFF) << 20;
177 prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
178
179 /* Get the configured protection IDs */
180 id = readl(&sdr_ctrl->prot_rule_id);
181 prule->lo_prot_id = id & 0xFFF;
182 prule->hi_prot_id = (id >> 12) & 0xFFF;
183
184 /* Get protection data */
185 data = readl(&sdr_ctrl->prot_rule_data);
186
187 prule->security = data & 0x3;
188 prule->valid = (data >> 2) & 0x1;
189 prule->portmask = (data >> 3) & 0x3FF;
190 prule->result = (data >> 13) & 0x1;
191 }
192
193 static void
sdram_set_protection_config(struct socfpga_sdr_ctrl * sdr_ctrl,const u32 sdram_start,const u32 sdram_end)194 sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl,
195 const u32 sdram_start, const u32 sdram_end)
196 {
197 struct sdram_prot_rule rule;
198 int rules;
199
200 /* Start with accepting all SDRAM transaction */
201 writel(0x0, &sdr_ctrl->protport_default);
202
203 /* Clear all protection rules for warm boot case */
204 memset(&rule, 0, sizeof(rule));
205
206 for (rules = 0; rules < 20; rules++) {
207 rule.rule = rules;
208 sdram_set_rule(sdr_ctrl, &rule);
209 }
210
211 /* new rule: accept SDRAM */
212 rule.sdram_start = sdram_start;
213 rule.sdram_end = sdram_end;
214 rule.lo_prot_id = 0x0;
215 rule.hi_prot_id = 0xFFF;
216 rule.portmask = 0x3FF;
217 rule.security = 0x3;
218 rule.result = 0;
219 rule.valid = 1;
220 rule.rule = 0;
221
222 /* set new rule */
223 sdram_set_rule(sdr_ctrl, &rule);
224
225 /* default rule: reject everything */
226 writel(0x3ff, &sdr_ctrl->protport_default);
227 }
228
sdram_dump_protection_config(struct socfpga_sdr_ctrl * sdr_ctrl)229 static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl)
230 {
231 struct sdram_prot_rule rule;
232 int rules;
233
234 debug("SDRAM Prot rule, default %x\n",
235 readl(&sdr_ctrl->protport_default));
236
237 for (rules = 0; rules < 20; rules++) {
238 rule.rule = rules;
239 sdram_get_rule(sdr_ctrl, &rule);
240 debug("Rule %d, rules ...\n", rules);
241 debug(" sdram start %x\n", rule.sdram_start);
242 debug(" sdram end %x\n", rule.sdram_end);
243 debug(" low prot id %d, hi prot id %d\n",
244 rule.lo_prot_id,
245 rule.hi_prot_id);
246 debug(" portmask %x\n", rule.portmask);
247 debug(" security %d\n", rule.security);
248 debug(" result %d\n", rule.result);
249 debug(" valid %d\n", rule.valid);
250 }
251 }
252
253 /**
254 * sdram_write_verify() - write to register and verify the write.
255 * @addr: Register address
256 * @val: Value to be written and verified
257 *
258 * This function writes to a register, reads back the value and compares
259 * the result with the written value to check if the data match.
260 */
sdram_write_verify(const u32 * addr,const u32 val)261 static unsigned sdram_write_verify(const u32 *addr, const u32 val)
262 {
263 u32 rval;
264
265 debug(" Write - Address 0x%p Data 0x%08x\n", addr, val);
266 writel(val, addr);
267
268 debug(" Read and verify...");
269 rval = readl(addr);
270 if (rval != val) {
271 debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
272 addr, val, rval);
273 return -EINVAL;
274 }
275
276 debug("correct!\n");
277 return 0;
278 }
279
280 /**
281 * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
282 * @cfg: SDRAM controller configuration data
283 *
284 * Return the value of DRAM CTRLCFG register.
285 */
sdr_get_ctrlcfg(const struct socfpga_sdram_config * cfg)286 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
287 {
288 const u32 csbits =
289 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
290 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
291 u32 addrorder =
292 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
293 SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
294
295 u32 ctrl_cfg = cfg->ctrl_cfg;
296
297 /*
298 * SDRAM Failure When Accessing Non-Existent Memory
299 * Set the addrorder field of the SDRAM control register
300 * based on the CSBITs setting.
301 */
302 if (csbits == 1) {
303 if (addrorder != 0)
304 debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
305 addrorder = 0;
306 } else if (csbits == 2) {
307 if (addrorder != 2)
308 debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
309 addrorder = 2;
310 }
311
312 ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
313 ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
314
315 return ctrl_cfg;
316 }
317
318 /**
319 * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
320 * @cfg: SDRAM controller configuration data
321 *
322 * Return the value of DRAM ADDRW register.
323 */
sdr_get_addr_rw(const struct socfpga_sdram_config * cfg)324 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
325 {
326 /*
327 * SDRAM Failure When Accessing Non-Existent Memory
328 * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
329 * log2(number of chip select bits). Since there's only
330 * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
331 * which is the same as "chip selects" - 1.
332 */
333 const int rows = get_errata_rows(cfg);
334 u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
335
336 return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
337 }
338
339 /**
340 * sdr_load_regs() - Load SDRAM controller registers
341 * @cfg: SDRAM controller configuration data
342 *
343 * This function loads the register values into the SDRAM controller block.
344 */
sdr_load_regs(struct socfpga_sdr_ctrl * sdr_ctrl,const struct socfpga_sdram_config * cfg)345 static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl,
346 const struct socfpga_sdram_config *cfg)
347 {
348 const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
349 const u32 dram_addrw = sdr_get_addr_rw(cfg);
350
351 debug("\nConfiguring CTRLCFG\n");
352 writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
353
354 debug("Configuring DRAMTIMING1\n");
355 writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
356
357 debug("Configuring DRAMTIMING2\n");
358 writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
359
360 debug("Configuring DRAMTIMING3\n");
361 writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
362
363 debug("Configuring DRAMTIMING4\n");
364 writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
365
366 debug("Configuring LOWPWRTIMING\n");
367 writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
368
369 debug("Configuring DRAMADDRW\n");
370 writel(dram_addrw, &sdr_ctrl->dram_addrw);
371
372 debug("Configuring DRAMIFWIDTH\n");
373 writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
374
375 debug("Configuring DRAMDEVWIDTH\n");
376 writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
377
378 debug("Configuring LOWPWREQ\n");
379 writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
380
381 debug("Configuring DRAMINTR\n");
382 writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
383
384 debug("Configuring STATICCFG\n");
385 writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
386
387 debug("Configuring CTRLWIDTH\n");
388 writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
389
390 debug("Configuring PORTCFG\n");
391 writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
392
393 debug("Configuring FIFOCFG\n");
394 writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
395
396 debug("Configuring MPPRIORITY\n");
397 writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
398
399 debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
400 writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
401 writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
402 writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
403 writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
404
405 debug("Configuring MPPACING_MPPACING_0\n");
406 writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
407 writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
408 writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
409 writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
410
411 debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
412 writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
413 writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
414 writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
415
416 debug("Configuring PHYCTRL_PHYCTRL_0\n");
417 writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
418
419 debug("Configuring CPORTWIDTH\n");
420 writel(cfg->cport_width, &sdr_ctrl->cport_width);
421
422 debug("Configuring CPORTWMAP\n");
423 writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
424
425 debug("Configuring CPORTRMAP\n");
426 writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
427
428 debug("Configuring RFIFOCMAP\n");
429 writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
430
431 debug("Configuring WFIFOCMAP\n");
432 writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
433
434 debug("Configuring CPORTRDWR\n");
435 writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
436
437 debug("Configuring DRAMODT\n");
438 writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
439
440 if (dram_is_ddr(3)) {
441 debug("Configuring EXTRATIME1\n");
442 writel(cfg->extratime1, &sdr_ctrl->extratime1);
443 }
444 }
445
446 /**
447 * sdram_mmr_init_full() - Function to initialize SDRAM MMR
448 * @sdr_phy_reg: Value of the PHY control register 0
449 *
450 * Initialize the SDRAM MMR.
451 */
sdram_mmr_init_full(struct socfpga_sdr_ctrl * sdr_ctrl,unsigned int sdr_phy_reg)452 int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
453 unsigned int sdr_phy_reg)
454 {
455 const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
456 const unsigned int rows =
457 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
458 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
459 int ret;
460
461 writel(rows,
462 socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
463
464 sdr_load_regs(sdr_ctrl, cfg);
465
466 /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
467 writel(cfg->fpgaport_rst,
468 socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(3));
469
470 /* only enable if the FPGA is programmed */
471 if (fpgamgr_test_fpga_ready()) {
472 ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
473 cfg->fpgaport_rst);
474 if (ret)
475 return ret;
476 }
477
478 /* Restore the SDR PHY Register if valid */
479 if (sdr_phy_reg != 0xffffffff)
480 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
481
482 /* Final step - apply configuration changes */
483 debug("Configuring STATICCFG\n");
484 clrsetbits_le32(&sdr_ctrl->static_cfg,
485 SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
486 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
487
488 sdram_set_protection_config(sdr_ctrl, 0,
489 sdram_calculate_size(sdr_ctrl) - 1);
490
491 sdram_dump_protection_config(sdr_ctrl);
492
493 return 0;
494 }
495
496 /**
497 * sdram_calculate_size() - Calculate SDRAM size
498 *
499 * Calculate SDRAM device size based on SDRAM controller parameters.
500 * Size is specified in bytes.
501 */
sdram_calculate_size(struct socfpga_sdr_ctrl * sdr_ctrl)502 static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
503 {
504 unsigned long temp;
505 unsigned long row, bank, col, cs, width;
506 const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
507 const unsigned int csbits =
508 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
509 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
510 const unsigned int rowbits =
511 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
512 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
513
514 temp = readl(&sdr_ctrl->dram_addrw);
515 col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
516 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
517
518 /*
519 * SDRAM Failure When Accessing Non-Existent Memory
520 * Use ROWBITS from Quartus/QSys to calculate SDRAM size
521 * since the FB specifies we modify ROWBITs to work around SDRAM
522 * controller issue.
523 */
524 row = readl(socfpga_get_sysmgr_addr() +
525 SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
526 if (row == 0)
527 row = rowbits;
528 /*
529 * If the stored handoff value for rows is greater than
530 * the field width in the sdr.dramaddrw register then
531 * something is very wrong. Revert to using the the #define
532 * value handed off by the SOCEDS tool chain instead of
533 * using a broken value.
534 */
535 if (row > 31)
536 row = rowbits;
537
538 bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
539 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
540
541 /*
542 * SDRAM Failure When Accessing Non-Existent Memory
543 * Use CSBITs from Quartus/QSys to calculate SDRAM size
544 * since the FB specifies we modify CSBITs to work around SDRAM
545 * controller issue.
546 */
547 cs = csbits;
548
549 width = readl(&sdr_ctrl->dram_if_width);
550
551 /* ECC would not be calculated as its not addressible */
552 if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
553 width = 32;
554 if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
555 width = 16;
556
557 /* calculate the SDRAM size base on this info */
558 temp = 1 << (row + bank + col);
559 temp = temp * cs * (width / 8);
560
561 debug("%s returns %ld\n", __func__, temp);
562
563 return temp;
564 }
565
altera_gen5_sdram_of_to_plat(struct udevice * dev)566 static int altera_gen5_sdram_of_to_plat(struct udevice *dev)
567 {
568 struct altera_gen5_sdram_plat *plat = dev_get_plat(dev);
569
570 plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
571 if (!plat->sdr)
572 return -ENODEV;
573
574 return 0;
575 }
576
altera_gen5_sdram_probe(struct udevice * dev)577 static int altera_gen5_sdram_probe(struct udevice *dev)
578 {
579 int ret;
580 unsigned long sdram_size;
581 struct altera_gen5_sdram_plat *plat = dev_get_plat(dev);
582 struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
583 struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl;
584 struct reset_ctl_bulk resets;
585
586 ret = reset_get_bulk(dev, &resets);
587 if (ret) {
588 dev_err(dev, "Can't get reset: %d\n", ret);
589 return -ENODEV;
590 }
591 reset_deassert_bulk(&resets);
592
593 if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) {
594 puts("SDRAM init failed.\n");
595 goto failed;
596 }
597
598 debug("SDRAM: Calibrating PHY\n");
599 /* SDRAM calibration */
600 if (sdram_calibration_full(plat->sdr) == 0) {
601 puts("SDRAM calibration failed.\n");
602 goto failed;
603 }
604
605 sdram_size = sdram_calculate_size(sdr_ctrl);
606 debug("SDRAM: %ld MiB\n", sdram_size >> 20);
607
608 /* Sanity check ensure correct SDRAM size specified */
609 if (get_ram_size(0, sdram_size) != sdram_size) {
610 puts("SDRAM size check failed!\n");
611 goto failed;
612 }
613
614 priv->info.base = 0;
615 priv->info.size = sdram_size;
616
617 return 0;
618
619 failed:
620 reset_release_bulk(&resets);
621 return -ENODEV;
622 }
623
altera_gen5_sdram_get_info(struct udevice * dev,struct ram_info * info)624 static int altera_gen5_sdram_get_info(struct udevice *dev,
625 struct ram_info *info)
626 {
627 struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
628
629 info->base = priv->info.base;
630 info->size = priv->info.size;
631
632 return 0;
633 }
634
635 static const struct ram_ops altera_gen5_sdram_ops = {
636 .get_info = altera_gen5_sdram_get_info,
637 };
638
639 static const struct udevice_id altera_gen5_sdram_ids[] = {
640 { .compatible = "altr,sdr-ctl" },
641 { /* sentinel */ }
642 };
643
644 U_BOOT_DRIVER(altera_gen5_sdram) = {
645 .name = "altr_sdr_ctl",
646 .id = UCLASS_RAM,
647 .of_match = altera_gen5_sdram_ids,
648 .ops = &altera_gen5_sdram_ops,
649 .of_to_plat = altera_gen5_sdram_of_to_plat,
650 .plat_auto = sizeof(struct altera_gen5_sdram_plat),
651 .probe = altera_gen5_sdram_probe,
652 .priv_auto = sizeof(struct altera_gen5_sdram_priv),
653 };
654
655 #endif /* CONFIG_SPL_BUILD */
656