1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Atmel I2C driver.
4 *
5 * (C) Copyright 2016 Songjun Wu <songjun.wu@atmel.com>
6 */
7
8 #include <malloc.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <common.h>
12 #include <clk.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <fdtdec.h>
16 #include <i2c.h>
17 #include <linux/bitops.h>
18 #include <mach/clk.h>
19
20 #include "at91_i2c.h"
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 #define I2C_TIMEOUT_MS 100
25
at91_wait_for_xfer(struct at91_i2c_bus * bus,u32 status)26 static int at91_wait_for_xfer(struct at91_i2c_bus *bus, u32 status)
27 {
28 struct at91_i2c_regs *reg = bus->regs;
29 ulong start_time = get_timer(0);
30 u32 sr;
31
32 bus->status = 0;
33
34 do {
35 sr = readl(®->sr);
36 bus->status |= sr;
37
38 if (sr & TWI_SR_NACK)
39 return -EREMOTEIO;
40 else if (sr & status)
41 return 0;
42 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
43
44 return -ETIMEDOUT;
45 }
46
at91_i2c_xfer_msg(struct at91_i2c_bus * bus,struct i2c_msg * msg)47 static int at91_i2c_xfer_msg(struct at91_i2c_bus *bus, struct i2c_msg *msg)
48 {
49 struct at91_i2c_regs *reg = bus->regs;
50 bool is_read = msg->flags & I2C_M_RD;
51 u32 i;
52 int ret = 0;
53
54 /* if there is no message to send/receive, just exit quietly */
55 if (msg->len == 0)
56 return ret;
57
58 readl(®->sr);
59 if (is_read) {
60 writel(TWI_CR_START, ®->cr);
61
62 for (i = 0; !ret && i < (msg->len - 1); i++) {
63 ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY);
64 msg->buf[i] = readl(®->rhr);
65 }
66
67 if (ret)
68 goto error;
69
70 writel(TWI_CR_STOP, ®->cr);
71
72 ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY);
73 if (ret)
74 goto error;
75
76 msg->buf[i] = readl(®->rhr);
77
78 } else {
79 writel(msg->buf[0], ®->thr);
80 ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY);
81
82 for (i = 1; !ret && (i < msg->len); i++) {
83 writel(msg->buf[i], ®->thr);
84 ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY);
85 }
86
87 if (ret)
88 goto error;
89
90 writel(TWI_CR_STOP, ®->cr);
91 }
92
93 if (!ret)
94 ret = at91_wait_for_xfer(bus, TWI_SR_TXCOMP);
95
96 if (ret)
97 goto error;
98
99 if (bus->status & (TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_LOCK)) {
100 ret = -EIO;
101 goto error;
102 }
103
104 return 0;
105
106 error:
107 if (bus->status & TWI_SR_LOCK)
108 writel(TWI_CR_LOCKCLR, ®->cr);
109
110 return ret;
111 }
112
at91_i2c_xfer(struct udevice * dev,struct i2c_msg * msg,int nmsgs)113 static int at91_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
114 {
115 struct at91_i2c_bus *bus = dev_get_priv(dev);
116 struct at91_i2c_regs *reg = bus->regs;
117 struct i2c_msg *m_start = msg;
118 bool is_read;
119 u32 int_addr_flag = 0;
120 int ret = 0;
121
122 if (nmsgs == 2) {
123 int internal_address = 0;
124 int i;
125
126 /* 1st msg is put into the internal address, start with 2nd */
127 m_start = &msg[1];
128
129 /* the max length of internal address is 3 bytes */
130 if (msg->len > 3)
131 return -EFAULT;
132
133 for (i = 0; i < msg->len; ++i) {
134 const unsigned addr = msg->buf[msg->len - 1 - i];
135
136 internal_address |= addr << (8 * i);
137 int_addr_flag += TWI_MMR_IADRSZ_1;
138 }
139
140 writel(internal_address, ®->iadr);
141 }
142
143 is_read = m_start->flags & I2C_M_RD;
144
145 writel((m_start->addr << 16) | int_addr_flag |
146 (is_read ? TWI_MMR_MREAD : 0), ®->mmr);
147
148 ret = at91_i2c_xfer_msg(bus, m_start);
149
150 return ret;
151 }
152
153 /*
154 * Calculate symmetric clock as stated in datasheet:
155 * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
156 */
at91_calc_i2c_clock(struct udevice * dev,int i2c_clk)157 static void at91_calc_i2c_clock(struct udevice *dev, int i2c_clk)
158 {
159 struct at91_i2c_bus *bus = dev_get_priv(dev);
160 const struct at91_i2c_pdata *pdata = bus->pdata;
161 int offset = pdata->clk_offset;
162 int max_ckdiv = pdata->clk_max_div;
163 int ckdiv, cdiv, div;
164 unsigned long src_rate;
165
166 src_rate = bus->bus_clk_rate;
167
168 div = max(0, (int)DIV_ROUND_UP(src_rate, 2 * i2c_clk) - offset);
169 ckdiv = fls(div >> 8);
170 cdiv = div >> ckdiv;
171
172 if (ckdiv > max_ckdiv) {
173 ckdiv = max_ckdiv;
174 cdiv = 255;
175 }
176
177 bus->speed = DIV_ROUND_UP(src_rate,
178 (cdiv * (1 << ckdiv) + offset) * 2);
179
180 bus->cwgr_val = (ckdiv << 16) | (cdiv << 8) | cdiv;
181 }
182
at91_i2c_enable_clk(struct udevice * dev)183 static int at91_i2c_enable_clk(struct udevice *dev)
184 {
185 struct at91_i2c_bus *bus = dev_get_priv(dev);
186 struct clk clk;
187 ulong clk_rate;
188 int ret;
189
190 ret = clk_get_by_index(dev, 0, &clk);
191 if (ret)
192 return -EINVAL;
193
194 ret = clk_enable(&clk);
195 if (ret)
196 return ret;
197
198 clk_rate = clk_get_rate(&clk);
199 if (!clk_rate)
200 return -EINVAL;
201
202 bus->bus_clk_rate = clk_rate;
203
204 clk_free(&clk);
205
206 return 0;
207 }
208
at91_i2c_set_bus_speed(struct udevice * dev,unsigned int speed)209 static int at91_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
210 {
211 struct at91_i2c_bus *bus = dev_get_priv(dev);
212
213 at91_calc_i2c_clock(dev, speed);
214
215 writel(bus->cwgr_val, &bus->regs->cwgr);
216
217 return 0;
218 }
219
at91_i2c_get_bus_speed(struct udevice * dev)220 int at91_i2c_get_bus_speed(struct udevice *dev)
221 {
222 struct at91_i2c_bus *bus = dev_get_priv(dev);
223
224 return bus->speed;
225 }
226
at91_i2c_of_to_plat(struct udevice * dev)227 static int at91_i2c_of_to_plat(struct udevice *dev)
228 {
229 const void *blob = gd->fdt_blob;
230 struct at91_i2c_bus *bus = dev_get_priv(dev);
231 int node = dev_of_offset(dev);
232
233 bus->regs = dev_read_addr_ptr(dev);
234 bus->pdata = (struct at91_i2c_pdata *)dev_get_driver_data(dev);
235 bus->clock_frequency = fdtdec_get_int(blob, node,
236 "clock-frequency", 100000);
237
238 return 0;
239 }
240
241 static const struct dm_i2c_ops at91_i2c_ops = {
242 .xfer = at91_i2c_xfer,
243 .set_bus_speed = at91_i2c_set_bus_speed,
244 .get_bus_speed = at91_i2c_get_bus_speed,
245 };
246
at91_i2c_probe(struct udevice * dev)247 static int at91_i2c_probe(struct udevice *dev)
248 {
249 struct at91_i2c_bus *bus = dev_get_priv(dev);
250 struct at91_i2c_regs *reg = bus->regs;
251 int ret;
252
253 ret = at91_i2c_enable_clk(dev);
254 if (ret)
255 return ret;
256
257 writel(TWI_CR_SWRST, ®->cr);
258
259 at91_calc_i2c_clock(dev, bus->clock_frequency);
260
261 writel(bus->cwgr_val, ®->cwgr);
262 writel(TWI_CR_MSEN, ®->cr);
263 writel(TWI_CR_SVDIS, ®->cr);
264
265 return 0;
266 }
267
268 static const struct at91_i2c_pdata at91rm9200_config = {
269 .clk_max_div = 5,
270 .clk_offset = 3,
271 };
272
273 static const struct at91_i2c_pdata at91sam9261_config = {
274 .clk_max_div = 5,
275 .clk_offset = 4,
276 };
277
278 static const struct at91_i2c_pdata at91sam9260_config = {
279 .clk_max_div = 7,
280 .clk_offset = 4,
281 };
282
283 static const struct at91_i2c_pdata at91sam9g20_config = {
284 .clk_max_div = 7,
285 .clk_offset = 4,
286 };
287
288 static const struct at91_i2c_pdata at91sam9g10_config = {
289 .clk_max_div = 7,
290 .clk_offset = 4,
291 };
292
293 static const struct at91_i2c_pdata at91sam9x5_config = {
294 .clk_max_div = 7,
295 .clk_offset = 4,
296 };
297
298 static const struct at91_i2c_pdata sama5d4_config = {
299 .clk_max_div = 7,
300 .clk_offset = 4,
301 };
302
303 static const struct at91_i2c_pdata sama5d2_config = {
304 .clk_max_div = 7,
305 .clk_offset = 3,
306 };
307
308 static const struct udevice_id at91_i2c_ids[] = {
309 { .compatible = "atmel,at91rm9200-i2c", .data = (long)&at91rm9200_config },
310 { .compatible = "atmel,at91sam9260-i2c", .data = (long)&at91sam9260_config },
311 { .compatible = "atmel,at91sam9261-i2c", .data = (long)&at91sam9261_config },
312 { .compatible = "atmel,at91sam9g20-i2c", .data = (long)&at91sam9g20_config },
313 { .compatible = "atmel,at91sam9g10-i2c", .data = (long)&at91sam9g10_config },
314 { .compatible = "atmel,at91sam9x5-i2c", .data = (long)&at91sam9x5_config },
315 { .compatible = "atmel,sama5d4-i2c", .data = (long)&sama5d4_config },
316 { .compatible = "atmel,sama5d2-i2c", .data = (long)&sama5d2_config },
317 { }
318 };
319
320 U_BOOT_DRIVER(i2c_at91) = {
321 .name = "i2c_at91",
322 .id = UCLASS_I2C,
323 .of_match = at91_i2c_ids,
324 .probe = at91_i2c_probe,
325 .of_to_plat = at91_i2c_of_to_plat,
326 .per_child_auto = sizeof(struct dm_i2c_chip),
327 .priv_auto = sizeof(struct at91_i2c_bus),
328 .ops = &at91_i2c_ops,
329 };
330