1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2013 Broadcom Corporation.
4 *
5 * NOTE: This driver should be converted to driver model before June 2017.
6 * Please see doc/driver-model/i2c-howto.rst for instructions.
7 */
8
9 #include <common.h>
10 #include <log.h>
11 #include <asm/io.h>
12 #include <linux/delay.h>
13 #include <linux/errno.h>
14 #include <asm/arch/sysmap.h>
15 #include <asm/kona-common/clk.h>
16 #include <i2c.h>
17
18 /* Hardware register offsets and field defintions */
19 #define CS_OFFSET 0x00000020
20 #define CS_ACK_SHIFT 3
21 #define CS_ACK_MASK 0x00000008
22 #define CS_ACK_CMD_GEN_START 0x00000000
23 #define CS_ACK_CMD_GEN_RESTART 0x00000001
24 #define CS_CMD_SHIFT 1
25 #define CS_CMD_CMD_NO_ACTION 0x00000000
26 #define CS_CMD_CMD_START_RESTART 0x00000001
27 #define CS_CMD_CMD_STOP 0x00000002
28 #define CS_EN_SHIFT 0
29 #define CS_EN_CMD_ENABLE_BSC 0x00000001
30
31 #define TIM_OFFSET 0x00000024
32 #define TIM_PRESCALE_SHIFT 6
33 #define TIM_P_SHIFT 3
34 #define TIM_NO_DIV_SHIFT 2
35 #define TIM_DIV_SHIFT 0
36
37 #define DAT_OFFSET 0x00000028
38
39 #define TOUT_OFFSET 0x0000002c
40
41 #define TXFCR_OFFSET 0x0000003c
42 #define TXFCR_FIFO_FLUSH_MASK 0x00000080
43 #define TXFCR_FIFO_EN_MASK 0x00000040
44
45 #define IER_OFFSET 0x00000044
46 #define IER_READ_COMPLETE_INT_MASK 0x00000010
47 #define IER_I2C_INT_EN_MASK 0x00000008
48 #define IER_FIFO_INT_EN_MASK 0x00000002
49 #define IER_NOACK_EN_MASK 0x00000001
50
51 #define ISR_OFFSET 0x00000048
52 #define ISR_RESERVED_MASK 0xffffff60
53 #define ISR_CMDBUSY_MASK 0x00000080
54 #define ISR_READ_COMPLETE_MASK 0x00000010
55 #define ISR_SES_DONE_MASK 0x00000008
56 #define ISR_ERR_MASK 0x00000004
57 #define ISR_TXFIFOEMPTY_MASK 0x00000002
58 #define ISR_NOACK_MASK 0x00000001
59
60 #define CLKEN_OFFSET 0x0000004c
61 #define CLKEN_AUTOSENSE_OFF_MASK 0x00000080
62 #define CLKEN_M_SHIFT 4
63 #define CLKEN_N_SHIFT 1
64 #define CLKEN_CLKEN_MASK 0x00000001
65
66 #define FIFO_STATUS_OFFSET 0x00000054
67 #define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004
68 #define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010
69
70 #define HSTIM_OFFSET 0x00000058
71 #define HSTIM_HS_MODE_MASK 0x00008000
72 #define HSTIM_HS_HOLD_SHIFT 10
73 #define HSTIM_HS_HIGH_PHASE_SHIFT 5
74 #define HSTIM_HS_SETUP_SHIFT 0
75
76 #define PADCTL_OFFSET 0x0000005c
77 #define PADCTL_PAD_OUT_EN_MASK 0x00000004
78
79 #define RXFCR_OFFSET 0x00000068
80 #define RXFCR_NACK_EN_SHIFT 7
81 #define RXFCR_READ_COUNT_SHIFT 0
82 #define RXFIFORDOUT_OFFSET 0x0000006c
83
84 /* Locally used constants */
85 #define MAX_RX_FIFO_SIZE 64U /* bytes */
86 #define MAX_TX_FIFO_SIZE 64U /* bytes */
87
88 #define I2C_TIMEOUT 100000 /* usecs */
89
90 #define WAIT_INT_CHK 100 /* usecs */
91 #if I2C_TIMEOUT % WAIT_INT_CHK
92 #error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK
93 #endif
94
95 /* Operations that can be commanded to the controller */
96 enum bcm_kona_cmd_t {
97 BCM_CMD_NOACTION = 0,
98 BCM_CMD_START,
99 BCM_CMD_RESTART,
100 BCM_CMD_STOP,
101 };
102
103 /* Internal divider settings for standard mode, fast mode and fast mode plus */
104 struct bus_speed_cfg {
105 uint8_t time_m; /* Number of cycles for setup time */
106 uint8_t time_n; /* Number of cycles for hold time */
107 uint8_t prescale; /* Prescale divider */
108 uint8_t time_p; /* Timing coefficient */
109 uint8_t no_div; /* Disable clock divider */
110 uint8_t time_div; /* Post-prescale divider */
111 };
112
113 static const struct bus_speed_cfg std_cfg_table[] = {
114 [IC_SPEED_MODE_STANDARD] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
115 [IC_SPEED_MODE_FAST] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
116 [IC_SPEED_MODE_FAST_PLUS] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
117 };
118
119 struct bcm_kona_i2c_dev {
120 void *base;
121 uint speed;
122 const struct bus_speed_cfg *std_cfg;
123 };
124
125 /* Keep these two defines in sync */
126 #define DEF_SPD I2C_SPEED_STANDARD_RATE
127 #define DEF_SPD_ENUM IC_SPEED_MODE_STANDARD
128
129 #define DEF_DEVICE(num) \
130 {(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
131
132 static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
133 #ifdef CONFIG_SYS_I2C_BASE0
134 DEF_DEVICE(0),
135 #endif
136 #ifdef CONFIG_SYS_I2C_BASE1
137 DEF_DEVICE(1),
138 #endif
139 #ifdef CONFIG_SYS_I2C_BASE2
140 DEF_DEVICE(2),
141 #endif
142 #ifdef CONFIG_SYS_I2C_BASE3
143 DEF_DEVICE(3),
144 #endif
145 #ifdef CONFIG_SYS_I2C_BASE4
146 DEF_DEVICE(4),
147 #endif
148 #ifdef CONFIG_SYS_I2C_BASE5
149 DEF_DEVICE(5),
150 #endif
151 };
152
153 #define I2C_M_TEN 0x0010 /* ten bit address */
154 #define I2C_M_RD 0x0001 /* read data */
155 #define I2C_M_NOSTART 0x4000 /* no restart between msgs */
156
157 struct kona_i2c_msg {
158 uint16_t addr;
159 uint16_t flags;
160 uint16_t len;
161 uint8_t *buf;
162 };
163
bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev * dev,enum bcm_kona_cmd_t cmd)164 static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
165 enum bcm_kona_cmd_t cmd)
166 {
167 debug("%s, %d\n", __func__, cmd);
168
169 switch (cmd) {
170 case BCM_CMD_NOACTION:
171 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
172 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
173 dev->base + CS_OFFSET);
174 break;
175
176 case BCM_CMD_START:
177 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
178 (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
179 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
180 dev->base + CS_OFFSET);
181 break;
182
183 case BCM_CMD_RESTART:
184 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
185 (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
186 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
187 dev->base + CS_OFFSET);
188 break;
189
190 case BCM_CMD_STOP:
191 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
192 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
193 dev->base + CS_OFFSET);
194 break;
195
196 default:
197 printf("Unknown command %d\n", cmd);
198 }
199 }
200
bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev * dev)201 static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
202 {
203 writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
204 dev->base + CLKEN_OFFSET);
205 }
206
bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev * dev)207 static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
208 {
209 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
210 dev->base + CLKEN_OFFSET);
211 }
212
213 /* Wait until at least one of the mask bit(s) are set */
wait_for_int_timeout(struct bcm_kona_i2c_dev * dev,unsigned long time_left,uint32_t mask)214 static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev,
215 unsigned long time_left,
216 uint32_t mask)
217 {
218 uint32_t status;
219
220 while (time_left) {
221 status = readl(dev->base + ISR_OFFSET);
222
223 if ((status & ~ISR_RESERVED_MASK) == 0) {
224 debug("Bogus I2C interrupt 0x%x\n", status);
225 continue;
226 }
227
228 /* Must flush the TX FIFO when NAK detected */
229 if (status & ISR_NOACK_MASK)
230 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
231 dev->base + TXFCR_OFFSET);
232
233 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
234
235 if (status & mask) {
236 /* We are done since one of the mask bits are set */
237 return time_left;
238 }
239 udelay(WAIT_INT_CHK);
240 time_left -= WAIT_INT_CHK;
241 }
242 return 0;
243 }
244
245 /* Send command to I2C bus */
bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev * dev,enum bcm_kona_cmd_t cmd)246 static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
247 enum bcm_kona_cmd_t cmd)
248 {
249 int rc = 0;
250 unsigned long time_left = I2C_TIMEOUT;
251
252 /* Send the command */
253 bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
254
255 /* Wait for transaction to finish or timeout */
256 time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
257
258 if (!time_left) {
259 printf("controller timed out\n");
260 rc = -ETIMEDOUT;
261 }
262
263 /* Clear command */
264 bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
265
266 return rc;
267 }
268
269 /* Read a single RX FIFO worth of data from the i2c bus */
bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev * dev,uint8_t * buf,unsigned int len,unsigned int last_byte_nak)270 static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
271 uint8_t *buf, unsigned int len,
272 unsigned int last_byte_nak)
273 {
274 unsigned long time_left = I2C_TIMEOUT;
275
276 /* Start the RX FIFO */
277 writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
278 (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET);
279
280 /* Wait for FIFO read to complete */
281 time_left =
282 wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK);
283
284 if (!time_left) {
285 printf("RX FIFO time out\n");
286 return -EREMOTEIO;
287 }
288
289 /* Read data from FIFO */
290 for (; len > 0; len--, buf++)
291 *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
292
293 return 0;
294 }
295
296 /* Read any amount of data using the RX FIFO from the i2c bus */
bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev * dev,struct kona_i2c_msg * msg)297 static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
298 struct kona_i2c_msg *msg)
299 {
300 unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
301 unsigned int last_byte_nak = 0;
302 unsigned int bytes_read = 0;
303 int rc;
304
305 uint8_t *tmp_buf = msg->buf;
306
307 while (bytes_read < msg->len) {
308 if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
309 last_byte_nak = 1; /* NAK last byte of transfer */
310 bytes_to_read = msg->len - bytes_read;
311 }
312
313 rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
314 last_byte_nak);
315 if (rc < 0)
316 return -EREMOTEIO;
317
318 bytes_read += bytes_to_read;
319 tmp_buf += bytes_to_read;
320 }
321
322 return 0;
323 }
324
325 /* Write a single byte of data to the i2c bus */
bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev * dev,uint8_t data,unsigned int nak_expected)326 static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
327 unsigned int nak_expected)
328 {
329 unsigned long time_left = I2C_TIMEOUT;
330 unsigned int nak_received;
331
332 /* Clear pending session done interrupt */
333 writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
334
335 /* Send one byte of data */
336 writel(data, dev->base + DAT_OFFSET);
337
338 time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
339
340 if (!time_left) {
341 debug("controller timed out\n");
342 return -ETIMEDOUT;
343 }
344
345 nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
346
347 if (nak_received ^ nak_expected) {
348 debug("unexpected NAK/ACK\n");
349 return -EREMOTEIO;
350 }
351
352 return 0;
353 }
354
355 /* Write a single TX FIFO worth of data to the i2c bus */
bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev * dev,uint8_t * buf,unsigned int len)356 static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
357 uint8_t *buf, unsigned int len)
358 {
359 int k;
360 unsigned long time_left = I2C_TIMEOUT;
361 unsigned int fifo_status;
362
363 /* Write data into FIFO */
364 for (k = 0; k < len; k++)
365 writel(buf[k], (dev->base + DAT_OFFSET));
366
367 /* Wait for FIFO to empty */
368 do {
369 time_left =
370 wait_for_int_timeout(dev, time_left,
371 (IER_FIFO_INT_EN_MASK |
372 IER_NOACK_EN_MASK));
373 fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
374 } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
375
376 /* Check if there was a NAK */
377 if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
378 printf("unexpected NAK\n");
379 return -EREMOTEIO;
380 }
381
382 /* Check if a timeout occurred */
383 if (!time_left) {
384 printf("completion timed out\n");
385 return -EREMOTEIO;
386 }
387
388 return 0;
389 }
390
391 /* Write any amount of data using TX FIFO to the i2c bus */
bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev * dev,struct kona_i2c_msg * msg)392 static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
393 struct kona_i2c_msg *msg)
394 {
395 unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
396 unsigned int bytes_written = 0;
397 int rc;
398
399 uint8_t *tmp_buf = msg->buf;
400
401 while (bytes_written < msg->len) {
402 if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
403 bytes_to_write = msg->len - bytes_written;
404
405 rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
406 bytes_to_write);
407 if (rc < 0)
408 return -EREMOTEIO;
409
410 bytes_written += bytes_to_write;
411 tmp_buf += bytes_to_write;
412 }
413
414 return 0;
415 }
416
417 /* Send i2c address */
bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev * dev,struct kona_i2c_msg * msg)418 static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
419 struct kona_i2c_msg *msg)
420 {
421 unsigned char addr;
422
423 if (msg->flags & I2C_M_TEN) {
424 /* First byte is 11110XX0 where XX is upper 2 bits */
425 addr = 0xf0 | ((msg->addr & 0x300) >> 7);
426 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
427 return -EREMOTEIO;
428
429 /* Second byte is the remaining 8 bits */
430 addr = msg->addr & 0xff;
431 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
432 return -EREMOTEIO;
433
434 if (msg->flags & I2C_M_RD) {
435 /* For read, send restart command */
436 if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
437 return -EREMOTEIO;
438
439 /* Then re-send the first byte with the read bit set */
440 addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01;
441 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
442 return -EREMOTEIO;
443 }
444 } else {
445 addr = msg->addr << 1;
446
447 if (msg->flags & I2C_M_RD)
448 addr |= 1;
449
450 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
451 return -EREMOTEIO;
452 }
453
454 return 0;
455 }
456
bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev * dev)457 static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
458 {
459 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
460 dev->base + CLKEN_OFFSET);
461 }
462
bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev * dev)463 static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
464 {
465 writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
466 dev->base + HSTIM_OFFSET);
467
468 writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
469 (dev->std_cfg->time_p << TIM_P_SHIFT) |
470 (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
471 (dev->std_cfg->time_div << TIM_DIV_SHIFT),
472 dev->base + TIM_OFFSET);
473
474 writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
475 (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
476 CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET);
477 }
478
479 /* Master transfer function */
bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev * dev,struct kona_i2c_msg msgs[],int num)480 static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev,
481 struct kona_i2c_msg msgs[], int num)
482 {
483 struct kona_i2c_msg *pmsg;
484 int rc = 0;
485 int i;
486
487 /* Enable pad output */
488 writel(0, dev->base + PADCTL_OFFSET);
489
490 /* Enable internal clocks */
491 bcm_kona_i2c_enable_clock(dev);
492
493 /* Send start command */
494 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
495 if (rc < 0) {
496 printf("Start command failed rc = %d\n", rc);
497 goto xfer_disable_pad;
498 }
499
500 /* Loop through all messages */
501 for (i = 0; i < num; i++) {
502 pmsg = &msgs[i];
503
504 /* Send restart for subsequent messages */
505 if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
506 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
507 if (rc < 0) {
508 printf("restart cmd failed rc = %d\n", rc);
509 goto xfer_send_stop;
510 }
511 }
512
513 /* Send slave address */
514 if (!(pmsg->flags & I2C_M_NOSTART)) {
515 rc = bcm_kona_i2c_do_addr(dev, pmsg);
516 if (rc < 0) {
517 debug("NAK from addr %2.2x msg#%d rc = %d\n",
518 pmsg->addr, i, rc);
519 goto xfer_send_stop;
520 }
521 }
522
523 /* Perform data transfer */
524 if (pmsg->flags & I2C_M_RD) {
525 rc = bcm_kona_i2c_read_fifo(dev, pmsg);
526 if (rc < 0) {
527 printf("read failure\n");
528 goto xfer_send_stop;
529 }
530 } else {
531 rc = bcm_kona_i2c_write_fifo(dev, pmsg);
532 if (rc < 0) {
533 printf("write failure");
534 goto xfer_send_stop;
535 }
536 }
537 }
538
539 rc = num;
540
541 xfer_send_stop:
542 /* Send a STOP command */
543 bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
544
545 xfer_disable_pad:
546 /* Disable pad output */
547 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
548
549 /* Stop internal clock */
550 bcm_kona_i2c_disable_clock(dev);
551
552 return rc;
553 }
554
bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev * dev,uint speed)555 static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev,
556 uint speed)
557 {
558 switch (speed) {
559 case I2C_SPEED_STANDARD_RATE:
560 dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_STANDARD];
561 break;
562 case I2C_SPEED_FAST_RATE:
563 dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST];
564 break;
565 case I2C_SPEED_FAST_PLUS_RATE:
566 dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST_PLUS];
567 break;
568 default:
569 printf("%d hz bus speed not supported\n", speed);
570 return -EINVAL;
571 }
572 dev->speed = speed;
573 return 0;
574 }
575
bcm_kona_i2c_init(struct bcm_kona_i2c_dev * dev)576 static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev)
577 {
578 /* Parse bus speed */
579 bcm_kona_i2c_assign_bus_speed(dev, dev->speed);
580
581 /* Enable internal clocks */
582 bcm_kona_i2c_enable_clock(dev);
583
584 /* Configure internal dividers */
585 bcm_kona_i2c_config_timing(dev);
586
587 /* Disable timeout */
588 writel(0, dev->base + TOUT_OFFSET);
589
590 /* Enable autosense */
591 bcm_kona_i2c_enable_autosense(dev);
592
593 /* Enable TX FIFO */
594 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
595 dev->base + TXFCR_OFFSET);
596
597 /* Mask all interrupts */
598 writel(0, dev->base + IER_OFFSET);
599
600 /* Clear all pending interrupts */
601 writel(ISR_CMDBUSY_MASK |
602 ISR_READ_COMPLETE_MASK |
603 ISR_SES_DONE_MASK |
604 ISR_ERR_MASK |
605 ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET);
606
607 /* Enable the controller but leave it idle */
608 bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
609
610 /* Disable pad output */
611 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
612 }
613
614 /*
615 * uboot layer
616 */
kona_get_dev(struct i2c_adapter * adap)617 struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap)
618 {
619 return &g_i2c_devs[adap->hwadapnr];
620 }
621
kona_i2c_init(struct i2c_adapter * adap,int speed,int slaveaddr)622 static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
623 {
624 struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
625
626 if (clk_bsc_enable(dev->base))
627 return;
628
629 bcm_kona_i2c_init(dev);
630 }
631
kona_i2c_read(struct i2c_adapter * adap,uchar chip,uint addr,int alen,uchar * buffer,int len)632 static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
633 int alen, uchar *buffer, int len)
634 {
635 /* msg[0] writes the addr, msg[1] reads the data */
636 struct kona_i2c_msg msg[2];
637 unsigned char msgbuf0[64];
638 struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
639
640 msg[0].addr = chip;
641 msg[0].flags = 0;
642 msg[0].len = 1;
643 msg[0].buf = msgbuf0; /* msgbuf0 contains incrementing reg addr */
644
645 msg[1].addr = chip;
646 msg[1].flags = I2C_M_RD;
647 /* msg[1].buf dest ptr increments each read */
648
649 msgbuf0[0] = (unsigned char)addr;
650 msg[1].buf = buffer;
651 msg[1].len = len;
652 if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) {
653 /* Sending 2 i2c messages */
654 kona_i2c_init(adap, adap->speed, adap->slaveaddr);
655 debug("I2C read: I/O error\n");
656 return -EIO;
657 }
658 return 0;
659 }
660
kona_i2c_write(struct i2c_adapter * adap,uchar chip,uint addr,int alen,uchar * buffer,int len)661 static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
662 int alen, uchar *buffer, int len)
663 {
664 struct kona_i2c_msg msg[1];
665 unsigned char msgbuf0[64];
666 unsigned int i;
667 struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
668
669 msg[0].addr = chip;
670 msg[0].flags = 0;
671 msg[0].len = 2; /* addr byte plus data */
672 msg[0].buf = msgbuf0;
673
674 for (i = 0; i < len; i++) {
675 msgbuf0[0] = addr++;
676 msgbuf0[1] = buffer[i];
677 if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) {
678 kona_i2c_init(adap, adap->speed, adap->slaveaddr);
679 debug("I2C write: I/O error\n");
680 return -EIO;
681 }
682 }
683 return 0;
684 }
685
kona_i2c_probe(struct i2c_adapter * adap,uchar chip)686 static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip)
687 {
688 uchar tmp;
689
690 /*
691 * read addr 0x0 of the given chip.
692 */
693 return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1);
694 }
695
kona_i2c_set_bus_speed(struct i2c_adapter * adap,uint speed)696 static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
697 {
698 struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
699 return bcm_kona_i2c_assign_bus_speed(dev, speed);
700 }
701
702 /*
703 * Register kona i2c adapters. Keep the order below so
704 * that the bus number matches the adapter number.
705 */
706 #define DEF_ADAPTER(num) \
707 U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \
708 kona_i2c_read, kona_i2c_write, \
709 kona_i2c_set_bus_speed, DEF_SPD, 0x00, num)
710
711 #ifdef CONFIG_SYS_I2C_BASE0
712 DEF_ADAPTER(0)
713 #endif
714 #ifdef CONFIG_SYS_I2C_BASE1
715 DEF_ADAPTER(1)
716 #endif
717 #ifdef CONFIG_SYS_I2C_BASE2
718 DEF_ADAPTER(2)
719 #endif
720 #ifdef CONFIG_SYS_I2C_BASE3
721 DEF_ADAPTER(3)
722 #endif
723 #ifdef CONFIG_SYS_I2C_BASE4
724 DEF_ADAPTER(4)
725 #endif
726 #ifdef CONFIG_SYS_I2C_BASE5
727 DEF_ADAPTER(5)
728 #endif
729