1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config TPL_MISC 26 bool "Enable Driver Model for Misc drivers in TPL" 27 depends on TPL_DM 28 help 29 Enable driver model for miscellaneous devices. This class is 30 used only for those do not fit other more general classes. A 31 set of generic read, write and ioctl methods may be used to 32 access the device. 33 34config ALTERA_SYSID 35 bool "Altera Sysid support" 36 depends on MISC 37 help 38 Select this to enable a sysid for Altera devices. Please find 39 details on the "Embedded Peripherals IP User Guide" of Altera. 40 41config ATSHA204A 42 bool "Support for Atmel ATSHA204A module" 43 depends on MISC 44 help 45 Enable support for I2C connected Atmel's ATSHA204A 46 CryptoAuthentication module found for example on the Turris Omnia 47 board. 48 49config ROCKCHIP_EFUSE 50 bool "Rockchip e-fuse support" 51 depends on MISC 52 help 53 Enable (read-only) access for the e-fuse block found in Rockchip 54 SoCs: accesses can either be made using byte addressing and a length 55 or through child-nodes that are generated based on the e-fuse map 56 retrieved from the DTS. 57 58 This driver currently supports the RK3399 only, but can easily be 59 extended (by porting the read function from the Linux kernel sources) 60 to support other recent Rockchip devices. 61 62config ROCKCHIP_OTP 63 bool "Rockchip OTP Support" 64 depends on MISC 65 help 66 Enable (read-only) access for the one-time-programmable memory block 67 found in Rockchip SoCs: accesses can either be made using byte 68 addressing and a length or through child-nodes that are generated 69 based on the e-fuse map retrieved from the DTS. 70 71config SIFIVE_OTP 72 bool "SiFive eMemory OTP driver" 73 depends on MISC 74 help 75 Enable support for reading and writing the eMemory OTP on the 76 SiFive SoCs. 77 78config VEXPRESS_CONFIG 79 bool "Enable support for Arm Versatile Express config bus" 80 depends on MISC 81 help 82 If you say Y here, you will get support for accessing the 83 configuration bus on the Arm Versatile Express boards via 84 a sysreg driver. 85 86config CMD_CROS_EC 87 bool "Enable crosec command" 88 depends on CROS_EC 89 help 90 Enable command-line access to the Chrome OS EC (Embedded 91 Controller). This provides the 'crosec' command which has 92 a number of sub-commands for performing EC tasks such as 93 updating its flash, accessing a small saved context area 94 and talking to the I2C bus behind the EC (if there is one). 95 96config CROS_EC 97 bool "Enable Chrome OS EC" 98 help 99 Enable access to the Chrome OS EC. This is a separate 100 microcontroller typically available on a SPI bus on Chromebooks. It 101 provides access to the keyboard, some internal storage and may 102 control access to the battery and main PMIC depending on the 103 device. You can use the 'crosec' command to access it. 104 105config SPL_CROS_EC 106 bool "Enable Chrome OS EC in SPL" 107 depends on SPL 108 help 109 Enable access to the Chrome OS EC in SPL. This is a separate 110 microcontroller typically available on a SPI bus on Chromebooks. It 111 provides access to the keyboard, some internal storage and may 112 control access to the battery and main PMIC depending on the 113 device. You can use the 'crosec' command to access it. 114 115config TPL_CROS_EC 116 bool "Enable Chrome OS EC in TPL" 117 depends on TPL 118 help 119 Enable access to the Chrome OS EC in TPL. This is a separate 120 microcontroller typically available on a SPI bus on Chromebooks. It 121 provides access to the keyboard, some internal storage and may 122 control access to the battery and main PMIC depending on the 123 device. You can use the 'crosec' command to access it. 124 125config CROS_EC_I2C 126 bool "Enable Chrome OS EC I2C driver" 127 depends on CROS_EC 128 help 129 Enable I2C access to the Chrome OS EC. This is used on older 130 ARM Chromebooks such as snow and spring before the standard bus 131 changed to SPI. The EC will accept commands across the I2C using 132 a special message protocol, and provide responses. 133 134config CROS_EC_LPC 135 bool "Enable Chrome OS EC LPC driver" 136 depends on CROS_EC 137 help 138 Enable I2C access to the Chrome OS EC. This is used on x86 139 Chromebooks such as link and falco. The keyboard is provided 140 through a legacy port interface, so on x86 machines the main 141 function of the EC is power and thermal management. 142 143config SPL_CROS_EC_LPC 144 bool "Enable Chrome OS EC LPC driver in SPL" 145 depends on CROS_EC 146 help 147 Enable I2C access to the Chrome OS EC. This is used on x86 148 Chromebooks such as link and falco. The keyboard is provided 149 through a legacy port interface, so on x86 machines the main 150 function of the EC is power and thermal management. 151 152config TPL_CROS_EC_LPC 153 bool "Enable Chrome OS EC LPC driver in TPL" 154 depends on CROS_EC 155 help 156 Enable I2C access to the Chrome OS EC. This is used on x86 157 Chromebooks such as link and falco. The keyboard is provided 158 through a legacy port interface, so on x86 machines the main 159 function of the EC is power and thermal management. 160 161config CROS_EC_SANDBOX 162 bool "Enable Chrome OS EC sandbox driver" 163 depends on CROS_EC && SANDBOX 164 help 165 Enable a sandbox emulation of the Chrome OS EC. This supports 166 keyboard (use the -l flag to enable the LCD), verified boot context, 167 EC flash read/write/erase support and a few other things. It is 168 enough to perform a Chrome OS verified boot on sandbox. 169 170config SPL_CROS_EC_SANDBOX 171 bool "Enable Chrome OS EC sandbox driver in SPL" 172 depends on SPL_CROS_EC && SANDBOX 173 help 174 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports 175 keyboard (use the -l flag to enable the LCD), verified boot context, 176 EC flash read/write/erase support and a few other things. It is 177 enough to perform a Chrome OS verified boot on sandbox. 178 179config TPL_CROS_EC_SANDBOX 180 bool "Enable Chrome OS EC sandbox driver in TPL" 181 depends on TPL_CROS_EC && SANDBOX 182 help 183 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports 184 keyboard (use the -l flag to enable the LCD), verified boot context, 185 EC flash read/write/erase support and a few other things. It is 186 enough to perform a Chrome OS verified boot on sandbox. 187 188config CROS_EC_SPI 189 bool "Enable Chrome OS EC SPI driver" 190 depends on CROS_EC 191 help 192 Enable SPI access to the Chrome OS EC. This is used on newer 193 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 194 provides a faster and more robust interface than I2C but the bugs 195 are less interesting. 196 197config DS4510 198 bool "Enable support for DS4510 CPU supervisor" 199 help 200 Enable support for the Maxim DS4510 CPU supervisor. It has an 201 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 202 and a configurable timer for the supervisor function. The device is 203 connected over I2C. 204 205config FSL_SEC_MON 206 bool "Enable FSL SEC_MON Driver" 207 help 208 Freescale Security Monitor block is responsible for monitoring 209 system states. 210 Security Monitor can be transitioned on any security failures, 211 like software violations or hardware security violations. 212 213config IRQ 214 bool "Intel Interrupt controller" 215 depends on X86 || SANDBOX 216 help 217 This enables support for Intel interrupt controllers, including ITSS. 218 Some devices have extra features, such as Apollo Lake. The 219 device has its own uclass since there are several operations 220 involved. 221 222config JZ4780_EFUSE 223 bool "Ingenic JZ4780 eFUSE support" 224 depends on ARCH_JZ47XX 225 help 226 This selects support for the eFUSE on Ingenic JZ4780 SoCs. 227 228config MXC_OCOTP 229 bool "Enable MXC OCOTP Driver" 230 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 231 default y 232 help 233 If you say Y here, you will get support for the One Time 234 Programmable memory pages that are stored on the some 235 Freescale i.MX processors. 236 237config NUVOTON_NCT6102D 238 bool "Enable Nuvoton NCT6102D Super I/O driver" 239 help 240 If you say Y here, you will get support for the Nuvoton 241 NCT6102D Super I/O driver. This can be used to enable or 242 disable the legacy UART, the watchdog or other devices 243 in the Nuvoton Super IO chips on X86 platforms. 244 245config P2SB 246 bool "Intel Primary to Sideband Bridge" 247 depends on X86 || SANDBOX 248 help 249 This enables support for the Intel Primary to Sideband Bridge, 250 abbreviated to P2SB. The P2SB is used to access various peripherals 251 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI 252 space. The space is segmented into different channels and peripherals 253 are accessed by device-specific means within those channels. Devices 254 should be added in the device tree as subnodes of the P2SB. A 255 Peripheral Channel Register? (PCR) API is provided to access those 256 devices - see pcr_readl(), etc. 257 258config SPL_P2SB 259 bool "Intel Primary to Sideband Bridge in SPL" 260 depends on SPL && (X86 || SANDBOX) 261 help 262 The Primary to Sideband Bridge is used to access various peripherals 263 through memory-mapped I/O in a large chunk of PCI space. The space is 264 segmented into different channels and peripherals are accessed by 265 device-specific means within those channels. Devices should be added 266 in the device tree as subnodes of the p2sb. 267 268config TPL_P2SB 269 bool "Intel Primary to Sideband Bridge in TPL" 270 depends on TPL && (X86 || SANDBOX) 271 help 272 The Primary to Sideband Bridge is used to access various peripherals 273 through memory-mapped I/O in a large chunk of PCI space. The space is 274 segmented into different channels and peripherals are accessed by 275 device-specific means within those channels. Devices should be added 276 in the device tree as subnodes of the p2sb. 277 278config PWRSEQ 279 bool "Enable power-sequencing drivers" 280 depends on DM 281 help 282 Power-sequencing drivers provide support for controlling power for 283 devices. They are typically referenced by a phandle from another 284 device. When the device is started up, its power sequence can be 285 initiated. 286 287config SPL_PWRSEQ 288 bool "Enable power-sequencing drivers for SPL" 289 depends on PWRSEQ 290 help 291 Power-sequencing drivers provide support for controlling power for 292 devices. They are typically referenced by a phandle from another 293 device. When the device is started up, its power sequence can be 294 initiated. 295 296config PCA9551_LED 297 bool "Enable PCA9551 LED driver" 298 help 299 Enable driver for PCA9551 LED controller. This controller 300 is connected via I2C. So I2C needs to be enabled. 301 302config PCA9551_I2C_ADDR 303 hex "I2C address of PCA9551 LED controller" 304 depends on PCA9551_LED 305 default 0x60 306 help 307 The I2C address of the PCA9551 LED controller. 308 309config STM32MP_FUSE 310 bool "Enable STM32MP fuse wrapper providing the fuse API" 311 depends on ARCH_STM32MP && MISC 312 default y if CMD_FUSE 313 help 314 If you say Y here, you will get support for the fuse API (OTP) 315 for STM32MP architecture. 316 This API is needed for CMD_FUSE. 317 318config STM32_RCC 319 bool "Enable RCC driver for the STM32 SoC's family" 320 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC 321 help 322 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control 323 block) is responsible of the management of the clock and reset 324 generation. 325 This driver is similar to an MFD driver in the Linux kernel. 326 327config TEGRA_CAR 328 bool "Enable support for the Tegra CAR driver" 329 depends on TEGRA_NO_BPMP 330 help 331 The Tegra CAR (Clock and Reset Controller) is a HW module that 332 controls almost all clocks and resets in a Tegra SoC. 333 334config TEGRA186_BPMP 335 bool "Enable support for the Tegra186 BPMP driver" 336 depends on TEGRA186 337 help 338 The Tegra BPMP (Boot and Power Management Processor) is a separate 339 auxiliary CPU embedded into Tegra to perform power management work, 340 and controls related features such as clocks, resets, power domains, 341 PMIC I2C bus, etc. This driver provides the core low-level 342 communication path by which feature-specific drivers (such as clock) 343 can make requests to the BPMP. This driver is similar to an MFD 344 driver in the Linux kernel. 345 346config TEST_DRV 347 bool "Enable support for test drivers" 348 default y if SANDBOX 349 help 350 This enables drivers and uclasses that provides a way of testing the 351 operations of memory allocation and driver/uclass methods in driver 352 model. This should only be enabled for testing as it is not useful for 353 anything else. 354 355config TWL4030_LED 356 bool "Enable TWL4030 LED controller" 357 help 358 Enable this to add support for the TWL4030 LED controller. 359 360config WINBOND_W83627 361 bool "Enable Winbond Super I/O driver" 362 help 363 If you say Y here, you will get support for the Winbond 364 W83627 Super I/O driver. This can be used to enable the 365 legacy UART or other devices in the Winbond Super IO chips 366 on X86 platforms. 367 368config QFW 369 bool 370 help 371 Hidden option to enable QEMU fw_cfg interface. This will be selected by 372 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 373 374config I2C_EEPROM 375 bool "Enable driver for generic I2C-attached EEPROMs" 376 depends on MISC 377 help 378 Enable a generic driver for EEPROMs attached via I2C. 379 380 381config SPL_I2C_EEPROM 382 bool "Enable driver for generic I2C-attached EEPROMs for SPL" 383 depends on MISC && SPL && SPL_DM 384 help 385 This option is an SPL-variant of the I2C_EEPROM option. 386 See the help of I2C_EEPROM for details. 387 388if I2C_EEPROM 389 390config SYS_I2C_EEPROM_ADDR 391 hex "Chip address of the EEPROM device" 392 default 0 393 394config SYS_I2C_EEPROM_BUS 395 int "I2C bus of the EEPROM device." 396 default 0 397 398config SYS_EEPROM_SIZE 399 int "Size in bytes of the EEPROM device" 400 default 256 401 402config SYS_EEPROM_PAGE_WRITE_BITS 403 int "Number of bits used to address bytes in a single page" 404 default 0 405 help 406 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 407 A 64 byte page, for example would require six bits. 408 409config SYS_EEPROM_PAGE_WRITE_DELAY_MS 410 int "Number of milliseconds to delay between page writes" 411 default 0 412 413config SYS_I2C_EEPROM_ADDR_LEN 414 int "Length in bytes of the EEPROM memory array address" 415 default 1 416 help 417 Note: This is NOT the chip address length! 418 419config SYS_I2C_EEPROM_ADDR_OVERFLOW 420 hex "EEPROM Address Overflow" 421 default 0 422 help 423 EEPROM chips that implement "address overflow" are ones 424 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 425 address and the extra bits end up in the "chip address" bit 426 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 427 byte chips. 428 429endif 430 431config GDSYS_RXAUI_CTRL 432 bool "Enable gdsys RXAUI control driver" 433 depends on MISC 434 help 435 Support gdsys FPGA's RXAUI control. 436 437config GDSYS_IOEP 438 bool "Enable gdsys IOEP driver" 439 depends on MISC 440 help 441 Support gdsys FPGA's IO endpoint driver. 442 443config MPC83XX_SERDES 444 bool "Enable MPC83xx serdes driver" 445 depends on MISC 446 help 447 Support for serdes found on MPC83xx SoCs. 448 449config FS_LOADER 450 bool "Enable loader driver for file system" 451 help 452 This is file system generic loader which can be used to load 453 the file image from the storage into target such as memory. 454 455 The consumer driver would then use this loader to program whatever, 456 ie. the FPGA device. 457 458config GDSYS_SOC 459 bool "Enable gdsys SOC driver" 460 depends on MISC 461 help 462 Support for gdsys IHS SOC, a simple bus associated with each gdsys 463 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose 464 register maps are contained within the FPGA's register map. 465 466config IHS_FPGA 467 bool "Enable IHS FPGA driver" 468 depends on MISC 469 help 470 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on 471 gdsys devices, which supply the majority of the functionality offered 472 by the devices. This driver supports both CON and CPU variants of the 473 devices, depending on the device tree entry. 474config ESM_K3 475 bool "Enable K3 ESM driver" 476 depends on ARCH_K3 477 help 478 Support ESM (Error Signaling Module) on TI K3 SoCs. 479 480config MICROCHIP_FLEXCOM 481 bool "Enable Microchip Flexcom driver" 482 depends on MISC 483 help 484 The Atmel Flexcom is just a wrapper which embeds a SPI controller, 485 an I2C controller and an USART. 486 Only one function can be used at a time and is chosen at boot time 487 according to the device tree. 488 489config K3_AVS0 490 depends on ARCH_K3 && SPL_DM_REGULATOR 491 bool "AVS class 0 support for K3 devices" 492 help 493 K3 devices have the optimized voltage values for the main voltage 494 domains stored in efuse within the VTM IP. This driver reads the 495 optimized voltage from the efuse, so that it can be programmed 496 to the PMIC on board. 497 498config ESM_PMIC 499 bool "Enable PMIC ESM driver" 500 depends on DM_PMIC 501 help 502 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used 503 typically to reboot the board in error condition. 504 505endmenu 506