1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013 Altera Corporation <www.altera.com>
4 */
5
6 #include <common.h>
7 #include <log.h>
8 #include <asm/arch/clock_manager.h>
9 #include <asm/arch/secure_reg_helper.h>
10 #include <asm/arch/system_manager.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <dwmmc.h>
14 #include <errno.h>
15 #include <fdtdec.h>
16 #include <asm/global_data.h>
17 #include <dm/device_compat.h>
18 #include <linux/intel-smc.h>
19 #include <linux/libfdt.h>
20 #include <linux/err.h>
21 #include <malloc.h>
22 #include <reset.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 struct socfpga_dwmci_plat {
27 struct mmc_config cfg;
28 struct mmc mmc;
29 };
30
31 /* socfpga implmentation specific driver private data */
32 struct dwmci_socfpga_priv_data {
33 struct dwmci_host host;
34 unsigned int drvsel;
35 unsigned int smplsel;
36 };
37
socfpga_dwmci_reset(struct udevice * dev)38 static void socfpga_dwmci_reset(struct udevice *dev)
39 {
40 struct reset_ctl_bulk reset_bulk;
41 int ret;
42
43 ret = reset_get_bulk(dev, &reset_bulk);
44 if (ret) {
45 dev_warn(dev, "Can't get reset: %d\n", ret);
46 return;
47 }
48
49 reset_deassert_bulk(&reset_bulk);
50 }
51
socfpga_dwmci_clksel(struct dwmci_host * host)52 static int socfpga_dwmci_clksel(struct dwmci_host *host)
53 {
54 struct dwmci_socfpga_priv_data *priv = host->priv;
55 u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
56 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
57
58 /* Disable SDMMC clock. */
59 clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
60 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
61
62 debug("%s: drvsel %d smplsel %d\n", __func__,
63 priv->drvsel, priv->smplsel);
64
65 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
66 int ret;
67
68 ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC,
69 sdmmc_mask);
70 if (ret) {
71 printf("DWMMC: Failed to set clksel via SMC call");
72 return ret;
73 }
74 #else
75 writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
76
77 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
78 readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
79 #endif
80
81 /* Enable SDMMC clock */
82 setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
83 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
84
85 return 0;
86 }
87
socfpga_dwmmc_get_clk_rate(struct udevice * dev)88 static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
89 {
90 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
91 struct dwmci_host *host = &priv->host;
92 #if CONFIG_IS_ENABLED(CLK)
93 struct clk clk;
94 int ret;
95
96 ret = clk_get_by_index(dev, 1, &clk);
97 if (ret)
98 return ret;
99
100 host->bus_hz = clk_get_rate(&clk);
101
102 clk_free(&clk);
103 #else
104 /* Fixed clock divide by 4 which due to the SDMMC wrapper */
105 host->bus_hz = cm_get_mmc_controller_clk_hz();
106 #endif
107 if (host->bus_hz == 0) {
108 printf("DWMMC: MMC clock is zero!");
109 return -EINVAL;
110 }
111
112 return 0;
113 }
114
socfpga_dwmmc_of_to_plat(struct udevice * dev)115 static int socfpga_dwmmc_of_to_plat(struct udevice *dev)
116 {
117 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
118 struct dwmci_host *host = &priv->host;
119 int fifo_depth;
120
121 fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
122 "fifo-depth", 0);
123 if (fifo_depth < 0) {
124 printf("DWMMC: Can't get FIFO depth\n");
125 return -EINVAL;
126 }
127
128 host->name = dev->name;
129 host->ioaddr = dev_read_addr_ptr(dev);
130 host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
131 "bus-width", 4);
132 host->clksel = socfpga_dwmci_clksel;
133
134 /*
135 * TODO(sjg@chromium.org): Remove the need for this hack.
136 * We only have one dwmmc block on gen5 SoCFPGA.
137 */
138 host->dev_index = 0;
139 host->fifoth_val = MSIZE(0x2) |
140 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
141 priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
142 "drvsel", 3);
143 priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
144 "smplsel", 0);
145 host->priv = priv;
146
147 return 0;
148 }
149
socfpga_dwmmc_probe(struct udevice * dev)150 static int socfpga_dwmmc_probe(struct udevice *dev)
151 {
152 #ifdef CONFIG_BLK
153 struct socfpga_dwmci_plat *plat = dev_get_plat(dev);
154 #endif
155 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
156 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
157 struct dwmci_host *host = &priv->host;
158 int ret;
159
160 ret = socfpga_dwmmc_get_clk_rate(dev);
161 if (ret)
162 return ret;
163
164 socfpga_dwmci_reset(dev);
165
166 #ifdef CONFIG_BLK
167 dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
168 host->mmc = &plat->mmc;
169 #else
170
171 ret = add_dwmci(host, host->bus_hz, 400000);
172 if (ret)
173 return ret;
174 #endif
175 host->mmc->priv = &priv->host;
176 upriv->mmc = host->mmc;
177 host->mmc->dev = dev;
178
179 return dwmci_probe(dev);
180 }
181
socfpga_dwmmc_bind(struct udevice * dev)182 static int socfpga_dwmmc_bind(struct udevice *dev)
183 {
184 #ifdef CONFIG_BLK
185 struct socfpga_dwmci_plat *plat = dev_get_plat(dev);
186 int ret;
187
188 ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
189 if (ret)
190 return ret;
191 #endif
192
193 return 0;
194 }
195
196 static const struct udevice_id socfpga_dwmmc_ids[] = {
197 { .compatible = "altr,socfpga-dw-mshc" },
198 { }
199 };
200
201 U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
202 .name = "socfpga_dwmmc",
203 .id = UCLASS_MMC,
204 .of_match = socfpga_dwmmc_ids,
205 .of_to_plat = socfpga_dwmmc_of_to_plat,
206 .ops = &dm_dwmci_ops,
207 .bind = socfpga_dwmmc_bind,
208 .probe = socfpga_dwmmc_probe,
209 .priv_auto = sizeof(struct dwmci_socfpga_priv_data),
210 .plat_auto = sizeof(struct socfpga_dwmci_plat),
211 };
212