1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011 Calxeda, Inc.
4 */
5
6 #include <common.h>
7 #include <malloc.h>
8 #include <net.h>
9 #include <linux/compiler.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <asm/io.h>
13
14 #define TX_NUM_DESC 1
15 #define RX_NUM_DESC 32
16
17 #define MAC_TIMEOUT (5*CONFIG_SYS_HZ)
18
19 #define ETH_BUF_SZ 2048
20 #define TX_BUF_SZ (ETH_BUF_SZ * TX_NUM_DESC)
21 #define RX_BUF_SZ (ETH_BUF_SZ * RX_NUM_DESC)
22
23 #define RXSTART 0x00000002
24 #define TXSTART 0x00002000
25
26 #define RXENABLE 0x00000004
27 #define TXENABLE 0x00000008
28
29 #define XGMAC_CONTROL_SPD 0x40000000
30 #define XGMAC_CONTROL_SPD_MASK 0x60000000
31 #define XGMAC_CONTROL_SARC 0x10000000
32 #define XGMAC_CONTROL_SARK_MASK 0x18000000
33 #define XGMAC_CONTROL_CAR 0x04000000
34 #define XGMAC_CONTROL_CAR_MASK 0x06000000
35 #define XGMAC_CONTROL_CAR_SHIFT 25
36 #define XGMAC_CONTROL_DP 0x01000000
37 #define XGMAC_CONTROL_WD 0x00800000
38 #define XGMAC_CONTROL_JD 0x00400000
39 #define XGMAC_CONTROL_JE 0x00100000
40 #define XGMAC_CONTROL_LM 0x00001000
41 #define XGMAC_CONTROL_IPC 0x00000400
42 #define XGMAC_CONTROL_ACS 0x00000080
43 #define XGMAC_CONTROL_DDIC 0x00000010
44 #define XGMAC_CONTROL_TE 0x00000008
45 #define XGMAC_CONTROL_RE 0x00000004
46
47 #define XGMAC_DMA_BUSMODE_RESET 0x00000001
48 #define XGMAC_DMA_BUSMODE_DSL 0x00000004
49 #define XGMAC_DMA_BUSMODE_DSL_MASK 0x0000007c
50 #define XGMAC_DMA_BUSMODE_DSL_SHIFT 2
51 #define XGMAC_DMA_BUSMODE_ATDS 0x00000080
52 #define XGMAC_DMA_BUSMODE_PBL_MASK 0x00003f00
53 #define XGMAC_DMA_BUSMODE_PBL_SHIFT 8
54 #define XGMAC_DMA_BUSMODE_FB 0x00010000
55 #define XGMAC_DMA_BUSMODE_USP 0x00800000
56 #define XGMAC_DMA_BUSMODE_8PBL 0x01000000
57 #define XGMAC_DMA_BUSMODE_AAL 0x02000000
58
59 #define XGMAC_DMA_AXIMODE_ENLPI 0x80000000
60 #define XGMAC_DMA_AXIMODE_MGK 0x40000000
61 #define XGMAC_DMA_AXIMODE_WROSR 0x00100000
62 #define XGMAC_DMA_AXIMODE_WROSR_MASK 0x00F00000
63 #define XGMAC_DMA_AXIMODE_WROSR_SHIFT 20
64 #define XGMAC_DMA_AXIMODE_RDOSR 0x00010000
65 #define XGMAC_DMA_AXIMODE_RDOSR_MASK 0x000F0000
66 #define XGMAC_DMA_AXIMODE_RDOSR_SHIFT 16
67 #define XGMAC_DMA_AXIMODE_AAL 0x00001000
68 #define XGMAC_DMA_AXIMODE_BLEN256 0x00000080
69 #define XGMAC_DMA_AXIMODE_BLEN128 0x00000040
70 #define XGMAC_DMA_AXIMODE_BLEN64 0x00000020
71 #define XGMAC_DMA_AXIMODE_BLEN32 0x00000010
72 #define XGMAC_DMA_AXIMODE_BLEN16 0x00000008
73 #define XGMAC_DMA_AXIMODE_BLEN8 0x00000004
74 #define XGMAC_DMA_AXIMODE_BLEN4 0x00000002
75 #define XGMAC_DMA_AXIMODE_UNDEF 0x00000001
76
77 #define XGMAC_CORE_OMR_RTC_SHIFT 3
78 #define XGMAC_CORE_OMR_RTC_MASK 0x00000018
79 #define XGMAC_CORE_OMR_RTC 0x00000010
80 #define XGMAC_CORE_OMR_RSF 0x00000020
81 #define XGMAC_CORE_OMR_DT 0x00000040
82 #define XGMAC_CORE_OMR_FEF 0x00000080
83 #define XGMAC_CORE_OMR_EFC 0x00000100
84 #define XGMAC_CORE_OMR_RFA_SHIFT 9
85 #define XGMAC_CORE_OMR_RFA_MASK 0x00000E00
86 #define XGMAC_CORE_OMR_RFD_SHIFT 12
87 #define XGMAC_CORE_OMR_RFD_MASK 0x00007000
88 #define XGMAC_CORE_OMR_TTC_SHIFT 16
89 #define XGMAC_CORE_OMR_TTC_MASK 0x00030000
90 #define XGMAC_CORE_OMR_TTC 0x00020000
91 #define XGMAC_CORE_OMR_FTF 0x00100000
92 #define XGMAC_CORE_OMR_TSF 0x00200000
93
94 #define FIFO_MINUS_1K 0x0
95 #define FIFO_MINUS_2K 0x1
96 #define FIFO_MINUS_3K 0x2
97 #define FIFO_MINUS_4K 0x3
98 #define FIFO_MINUS_6K 0x4
99 #define FIFO_MINUS_8K 0x5
100 #define FIFO_MINUS_12K 0x6
101 #define FIFO_MINUS_16K 0x7
102
103 #define XGMAC_CORE_FLOW_PT_SHIFT 16
104 #define XGMAC_CORE_FLOW_PT_MASK 0xFFFF0000
105 #define XGMAC_CORE_FLOW_PT 0x00010000
106 #define XGMAC_CORE_FLOW_DZQP 0x00000080
107 #define XGMAC_CORE_FLOW_PLT_SHIFT 4
108 #define XGMAC_CORE_FLOW_PLT_MASK 0x00000030
109 #define XGMAC_CORE_FLOW_PLT 0x00000010
110 #define XGMAC_CORE_FLOW_UP 0x00000008
111 #define XGMAC_CORE_FLOW_RFE 0x00000004
112 #define XGMAC_CORE_FLOW_TFE 0x00000002
113 #define XGMAC_CORE_FLOW_FCB 0x00000001
114
115 /* XGMAC Descriptor Defines */
116 #define MAX_DESC_BUF_SZ (0x2000 - 8)
117
118 #define RXDESC_EXT_STATUS 0x00000001
119 #define RXDESC_CRC_ERR 0x00000002
120 #define RXDESC_RX_ERR 0x00000008
121 #define RXDESC_RX_WDOG 0x00000010
122 #define RXDESC_FRAME_TYPE 0x00000020
123 #define RXDESC_GIANT_FRAME 0x00000080
124 #define RXDESC_LAST_SEG 0x00000100
125 #define RXDESC_FIRST_SEG 0x00000200
126 #define RXDESC_VLAN_FRAME 0x00000400
127 #define RXDESC_OVERFLOW_ERR 0x00000800
128 #define RXDESC_LENGTH_ERR 0x00001000
129 #define RXDESC_SA_FILTER_FAIL 0x00002000
130 #define RXDESC_DESCRIPTOR_ERR 0x00004000
131 #define RXDESC_ERROR_SUMMARY 0x00008000
132 #define RXDESC_FRAME_LEN_OFFSET 16
133 #define RXDESC_FRAME_LEN_MASK 0x3fff0000
134 #define RXDESC_DA_FILTER_FAIL 0x40000000
135
136 #define RXDESC1_END_RING 0x00008000
137
138 #define RXDESC_IP_PAYLOAD_MASK 0x00000003
139 #define RXDESC_IP_PAYLOAD_UDP 0x00000001
140 #define RXDESC_IP_PAYLOAD_TCP 0x00000002
141 #define RXDESC_IP_PAYLOAD_ICMP 0x00000003
142 #define RXDESC_IP_HEADER_ERR 0x00000008
143 #define RXDESC_IP_PAYLOAD_ERR 0x00000010
144 #define RXDESC_IPV4_PACKET 0x00000040
145 #define RXDESC_IPV6_PACKET 0x00000080
146 #define TXDESC_UNDERFLOW_ERR 0x00000001
147 #define TXDESC_JABBER_TIMEOUT 0x00000002
148 #define TXDESC_LOCAL_FAULT 0x00000004
149 #define TXDESC_REMOTE_FAULT 0x00000008
150 #define TXDESC_VLAN_FRAME 0x00000010
151 #define TXDESC_FRAME_FLUSHED 0x00000020
152 #define TXDESC_IP_HEADER_ERR 0x00000040
153 #define TXDESC_PAYLOAD_CSUM_ERR 0x00000080
154 #define TXDESC_ERROR_SUMMARY 0x00008000
155 #define TXDESC_SA_CTRL_INSERT 0x00040000
156 #define TXDESC_SA_CTRL_REPLACE 0x00080000
157 #define TXDESC_2ND_ADDR_CHAINED 0x00100000
158 #define TXDESC_END_RING 0x00200000
159 #define TXDESC_CSUM_IP 0x00400000
160 #define TXDESC_CSUM_IP_PAYLD 0x00800000
161 #define TXDESC_CSUM_ALL 0x00C00000
162 #define TXDESC_CRC_EN_REPLACE 0x01000000
163 #define TXDESC_CRC_EN_APPEND 0x02000000
164 #define TXDESC_DISABLE_PAD 0x04000000
165 #define TXDESC_FIRST_SEG 0x10000000
166 #define TXDESC_LAST_SEG 0x20000000
167 #define TXDESC_INTERRUPT 0x40000000
168
169 #define DESC_OWN 0x80000000
170 #define DESC_BUFFER1_SZ_MASK 0x00001fff
171 #define DESC_BUFFER2_SZ_MASK 0x1fff0000
172 #define DESC_BUFFER2_SZ_OFFSET 16
173
174 struct xgmac_regs {
175 u32 config;
176 u32 framefilter;
177 u32 resv_1[4];
178 u32 flow_control;
179 u32 vlantag;
180 u32 version;
181 u32 vlaninclude;
182 u32 resv_2[2];
183 u32 pacestretch;
184 u32 vlanhash;
185 u32 resv_3;
186 u32 intreg;
187 struct {
188 u32 hi; /* 0x40 */
189 u32 lo; /* 0x44 */
190 } macaddr[16];
191 u32 resv_4[0xd0];
192 u32 core_opmode; /* 0x400 */
193 u32 resv_5[0x2bf];
194 u32 busmode; /* 0xf00 */
195 u32 txpoll;
196 u32 rxpoll;
197 u32 rxdesclist;
198 u32 txdesclist;
199 u32 dma_status;
200 u32 dma_opmode;
201 u32 intenable;
202 u32 resv_6[2];
203 u32 axi_mode; /* 0xf28 */
204 };
205
206 struct xgmac_dma_desc {
207 __le32 flags;
208 __le32 buf_size;
209 __le32 buf1_addr; /* Buffer 1 Address Pointer */
210 __le32 buf2_addr; /* Buffer 2 Address Pointer */
211 __le32 ext_status;
212 __le32 res[3];
213 };
214
215 /* XGMAC Descriptor Access Helpers */
desc_set_buf_len(struct xgmac_dma_desc * p,u32 buf_sz)216 static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
217 {
218 if (buf_sz > MAX_DESC_BUF_SZ)
219 p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
220 (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
221 else
222 p->buf_size = cpu_to_le32(buf_sz);
223 }
224
desc_get_buf_len(struct xgmac_dma_desc * p)225 static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
226 {
227 u32 len = le32_to_cpu(p->buf_size);
228 return (len & DESC_BUFFER1_SZ_MASK) +
229 ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
230 }
231
desc_init_rx_desc(struct xgmac_dma_desc * p,int ring_size,int buf_sz)232 static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
233 int buf_sz)
234 {
235 struct xgmac_dma_desc *end = p + ring_size - 1;
236
237 memset(p, 0, sizeof(*p) * ring_size);
238
239 for (; p <= end; p++)
240 desc_set_buf_len(p, buf_sz);
241
242 end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
243 }
244
desc_init_tx_desc(struct xgmac_dma_desc * p,u32 ring_size)245 static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
246 {
247 memset(p, 0, sizeof(*p) * ring_size);
248 p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
249 }
250
desc_get_owner(struct xgmac_dma_desc * p)251 static inline int desc_get_owner(struct xgmac_dma_desc *p)
252 {
253 return le32_to_cpu(p->flags) & DESC_OWN;
254 }
255
desc_set_rx_owner(struct xgmac_dma_desc * p)256 static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
257 {
258 /* Clear all fields and set the owner */
259 p->flags = cpu_to_le32(DESC_OWN);
260 }
261
desc_set_tx_owner(struct xgmac_dma_desc * p,u32 flags)262 static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
263 {
264 u32 tmpflags = le32_to_cpu(p->flags);
265 tmpflags &= TXDESC_END_RING;
266 tmpflags |= flags | DESC_OWN;
267 p->flags = cpu_to_le32(tmpflags);
268 }
269
desc_get_buf_addr(struct xgmac_dma_desc * p)270 static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p)
271 {
272 return (void *)le32_to_cpu(p->buf1_addr);
273 }
274
desc_set_buf_addr(struct xgmac_dma_desc * p,void * paddr,int len)275 static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
276 void *paddr, int len)
277 {
278 p->buf1_addr = cpu_to_le32(paddr);
279 if (len > MAX_DESC_BUF_SZ)
280 p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
281 }
282
desc_set_buf_addr_and_size(struct xgmac_dma_desc * p,void * paddr,int len)283 static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
284 void *paddr, int len)
285 {
286 desc_set_buf_len(p, len);
287 desc_set_buf_addr(p, paddr, len);
288 }
289
desc_get_rx_frame_len(struct xgmac_dma_desc * p)290 static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
291 {
292 u32 data = le32_to_cpu(p->flags);
293 u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
294 if (data & RXDESC_FRAME_TYPE)
295 len -= 4;
296
297 return len;
298 }
299
300 struct calxeda_eth_dev {
301 struct xgmac_dma_desc rx_chain[RX_NUM_DESC];
302 struct xgmac_dma_desc tx_chain[TX_NUM_DESC];
303 char rxbuffer[RX_BUF_SZ];
304
305 u32 tx_currdesc;
306 u32 rx_currdesc;
307
308 struct eth_device *dev;
309 } __aligned(32);
310
311 /*
312 * Initialize a descriptor ring. Calxeda XGMAC is configured to use
313 * advanced descriptors.
314 */
315
init_rx_desc(struct calxeda_eth_dev * priv)316 static void init_rx_desc(struct calxeda_eth_dev *priv)
317 {
318 struct xgmac_dma_desc *rxdesc = priv->rx_chain;
319 struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
320 void *rxbuffer = priv->rxbuffer;
321 int i;
322
323 desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ);
324 writel((ulong)rxdesc, ®s->rxdesclist);
325
326 for (i = 0; i < RX_NUM_DESC; i++) {
327 desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ),
328 ETH_BUF_SZ);
329 desc_set_rx_owner(rxdesc + i);
330 }
331 }
332
init_tx_desc(struct calxeda_eth_dev * priv)333 static void init_tx_desc(struct calxeda_eth_dev *priv)
334 {
335 struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
336
337 desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC);
338 writel((ulong)priv->tx_chain, ®s->txdesclist);
339 }
340
xgmac_reset(struct eth_device * dev)341 static int xgmac_reset(struct eth_device *dev)
342 {
343 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
344 int timeout = MAC_TIMEOUT;
345 u32 value;
346
347 value = readl(®s->config) & XGMAC_CONTROL_SPD_MASK;
348
349 writel(XGMAC_DMA_BUSMODE_RESET, ®s->busmode);
350 while ((timeout-- >= 0) &&
351 (readl(®s->busmode) & XGMAC_DMA_BUSMODE_RESET))
352 udelay(1);
353
354 writel(value, ®s->config);
355
356 return timeout;
357 }
358
xgmac_hwmacaddr(struct eth_device * dev)359 static void xgmac_hwmacaddr(struct eth_device *dev)
360 {
361 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
362 u32 macaddr[2];
363
364 memcpy(macaddr, dev->enetaddr, 6);
365 writel(macaddr[1], ®s->macaddr[0].hi);
366 writel(macaddr[0], ®s->macaddr[0].lo);
367 }
368
xgmac_init(struct eth_device * dev,struct bd_info * bis)369 static int xgmac_init(struct eth_device *dev, struct bd_info * bis)
370 {
371 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
372 struct calxeda_eth_dev *priv = dev->priv;
373 int value;
374
375 if (xgmac_reset(dev) < 0)
376 return -1;
377
378 /* set the hardware MAC address */
379 xgmac_hwmacaddr(dev);
380
381 /* set the AXI bus modes */
382 value = XGMAC_DMA_BUSMODE_ATDS |
383 (16 << XGMAC_DMA_BUSMODE_PBL_SHIFT) |
384 XGMAC_DMA_BUSMODE_FB | XGMAC_DMA_BUSMODE_AAL;
385 writel(value, ®s->busmode);
386
387 value = XGMAC_DMA_AXIMODE_AAL | XGMAC_DMA_AXIMODE_BLEN16 |
388 XGMAC_DMA_AXIMODE_BLEN8 | XGMAC_DMA_AXIMODE_BLEN4;
389 writel(value, ®s->axi_mode);
390
391 /* set flow control parameters and store and forward mode */
392 value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) |
393 (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) |
394 XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF;
395 writel(value, ®s->core_opmode);
396
397 /* enable pause frames */
398 value = (1024 << XGMAC_CORE_FLOW_PT_SHIFT) |
399 (1 << XGMAC_CORE_FLOW_PLT_SHIFT) |
400 XGMAC_CORE_FLOW_UP | XGMAC_CORE_FLOW_RFE | XGMAC_CORE_FLOW_TFE;
401 writel(value, ®s->flow_control);
402
403 /* Initialize the descriptor chains */
404 init_rx_desc(priv);
405 init_tx_desc(priv);
406
407 /* must set to 0, or when started up will cause issues */
408 priv->tx_currdesc = 0;
409 priv->rx_currdesc = 0;
410
411 /* set default core values */
412 value = readl(®s->config);
413 value &= XGMAC_CONTROL_SPD_MASK;
414 value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS |
415 XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR;
416
417 /* Everything is ready enable both mac and DMA */
418 value |= RXENABLE | TXENABLE;
419 writel(value, ®s->config);
420
421 value = readl(®s->dma_opmode);
422 value |= RXSTART | TXSTART;
423 writel(value, ®s->dma_opmode);
424
425 return 0;
426 }
427
xgmac_tx(struct eth_device * dev,void * packet,int length)428 static int xgmac_tx(struct eth_device *dev, void *packet, int length)
429 {
430 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
431 struct calxeda_eth_dev *priv = dev->priv;
432 u32 currdesc = priv->tx_currdesc;
433 struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc];
434 int timeout;
435
436 desc_set_buf_addr_and_size(txdesc, packet, length);
437 desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG |
438 TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND);
439
440 /* write poll demand */
441 writel(1, ®s->txpoll);
442
443 timeout = 1000000;
444 while (desc_get_owner(txdesc)) {
445 if (timeout-- < 0) {
446 printf("xgmac: TX timeout\n");
447 return -ETIMEDOUT;
448 }
449 udelay(1);
450 }
451
452 priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1);
453 return 0;
454 }
455
xgmac_rx(struct eth_device * dev)456 static int xgmac_rx(struct eth_device *dev)
457 {
458 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
459 struct calxeda_eth_dev *priv = dev->priv;
460 u32 currdesc = priv->rx_currdesc;
461 struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc];
462 int length = 0;
463
464 /* check if the host has the desc */
465 if (desc_get_owner(rxdesc))
466 return -1; /* something bad happened */
467
468 length = desc_get_rx_frame_len(rxdesc);
469
470 net_process_received_packet(desc_get_buf_addr(rxdesc), length);
471
472 /* set descriptor back to owned by XGMAC */
473 desc_set_rx_owner(rxdesc);
474 writel(1, ®s->rxpoll);
475
476 priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1);
477
478 return length;
479 }
480
xgmac_halt(struct eth_device * dev)481 static void xgmac_halt(struct eth_device *dev)
482 {
483 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
484 struct calxeda_eth_dev *priv = dev->priv;
485 int value;
486
487 /* Disable TX/RX */
488 value = readl(®s->config);
489 value &= ~(RXENABLE | TXENABLE);
490 writel(value, ®s->config);
491
492 /* Disable DMA */
493 value = readl(®s->dma_opmode);
494 value &= ~(RXSTART | TXSTART);
495 writel(value, ®s->dma_opmode);
496
497 /* must set to 0, or when started up will cause issues */
498 priv->tx_currdesc = 0;
499 priv->rx_currdesc = 0;
500 }
501
calxedaxgmac_initialize(u32 id,ulong base_addr)502 int calxedaxgmac_initialize(u32 id, ulong base_addr)
503 {
504 struct eth_device *dev;
505 struct calxeda_eth_dev *priv;
506 struct xgmac_regs *regs;
507 u32 macaddr[2];
508
509 regs = (struct xgmac_regs *)base_addr;
510
511 /* check hardware version */
512 if (readl(®s->version) != 0x1012)
513 return -1;
514
515 dev = malloc(sizeof(*dev));
516 if (!dev)
517 return 0;
518 memset(dev, 0, sizeof(*dev));
519
520 /* Structure must be aligned, because it contains the descriptors */
521 priv = memalign(32, sizeof(*priv));
522 if (!priv) {
523 free(dev);
524 return 0;
525 }
526
527 dev->iobase = (int)base_addr;
528 dev->priv = priv;
529 priv->dev = dev;
530 sprintf(dev->name, "xgmac%d", id);
531
532 /* The MAC address is already configured, so read it from registers. */
533 macaddr[1] = readl(®s->macaddr[0].hi);
534 macaddr[0] = readl(®s->macaddr[0].lo);
535 memcpy(dev->enetaddr, macaddr, 6);
536
537 dev->init = xgmac_init;
538 dev->send = xgmac_tx;
539 dev->recv = xgmac_rx;
540 dev->halt = xgmac_halt;
541
542 eth_register(dev);
543
544 return 1;
545 }
546