1 /*
2 ns8382x.c: A U-Boot driver for the NatSemi DP8382[01].
3 ported by: Mark A. Rakes (mark_rakes@vivato.net)
4
5 Adapted from:
6 1. an Etherboot driver for DP8381[56] written by:
7 Copyright (C) 2001 Entity Cyber, Inc.
8
9 This development of this Etherboot driver was funded by
10 Sicom Systems: http://www.sicompos.com/
11
12 Author: Marty Connor (mdc@thinguin.org)
13 Adapted from a Linux driver which was written by Donald Becker
14
15 This software may be used and distributed according to the terms
16 of the GNU Public License (GPL), incorporated herein by reference.
17
18 2. A Linux driver by Donald Becker, ns820.c:
19 Written/copyright 1999-2002 by Donald Becker.
20
21 This software may be used and distributed according to the terms of
22 the GNU General Public License (GPL), incorporated herein by reference.
23 Drivers based on or derived from this code fall under the GPL and must
24 retain the authorship, copyright and license notice. This file is not
25 a complete program and may only be used when the entire operating
26 system is licensed under the GPL. License for under other terms may be
27 available. Contact the original author for details.
28
29 The original author may be reached as becker@scyld.com, or at
30 Scyld Computing Corporation
31 410 Severn Ave., Suite 210
32 Annapolis MD 21403
33
34 Support information and updates available at
35 http://www.scyld.com/network/netsemi.html
36
37 Datasheets available from:
38 http://www.national.com/pf/DP/DP83820.html
39 http://www.national.com/pf/DP/DP83821.html
40 */
41
42 /* Revision History
43 * October 2002 mar 1.0
44 * Initial U-Boot Release.
45 * Tested with Netgear GA622T (83820)
46 * and SMC9452TX (83821)
47 * NOTE: custom boards with these chips may (likely) require
48 * a programmed EEPROM device (if present) in order to work
49 * correctly.
50 */
51
52 /* Includes */
53 #include <common.h>
54 #include <log.h>
55 #include <malloc.h>
56 #include <net.h>
57 #include <netdev.h>
58 #include <asm/io.h>
59 #include <pci.h>
60 #include <linux/delay.h>
61
62 /* defines */
63 #define DSIZE 0x00000FFF
64 #define CRC_SIZE 4
65 #define TOUT_LOOP 500000
66 #define TX_BUF_SIZE 1536
67 #define RX_BUF_SIZE 1536
68 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
69
70 enum register_offsets {
71 ChipCmd = 0x00,
72 ChipConfig = 0x04,
73 EECtrl = 0x08,
74 IntrMask = 0x14,
75 IntrEnable = 0x18,
76 TxRingPtr = 0x20,
77 TxRingPtrHi = 0x24,
78 TxConfig = 0x28,
79 RxRingPtr = 0x30,
80 RxRingPtrHi = 0x34,
81 RxConfig = 0x38,
82 PriQueue = 0x3C,
83 RxFilterAddr = 0x48,
84 RxFilterData = 0x4C,
85 ClkRun = 0xCC,
86 PCIPM = 0x44,
87 };
88
89 enum ChipCmdBits {
90 ChipReset = 0x100,
91 RxReset = 0x20,
92 TxReset = 0x10,
93 RxOff = 0x08,
94 RxOn = 0x04,
95 TxOff = 0x02,
96 TxOn = 0x01
97 };
98
99 enum ChipConfigBits {
100 LinkSts = 0x80000000,
101 GigSpeed = 0x40000000,
102 HundSpeed = 0x20000000,
103 FullDuplex = 0x10000000,
104 TBIEn = 0x01000000,
105 Mode1000 = 0x00400000,
106 T64En = 0x00004000,
107 D64En = 0x00001000,
108 M64En = 0x00000800,
109 PhyRst = 0x00000400,
110 PhyDis = 0x00000200,
111 ExtStEn = 0x00000100,
112 BEMode = 0x00000001,
113 };
114 #define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex)
115
116 enum TxConfig_bits {
117 TxDrthMask = 0x000000ff,
118 TxFlthMask = 0x0000ff00,
119 TxMxdmaMask = 0x00700000,
120 TxMxdma_8 = 0x00100000,
121 TxMxdma_16 = 0x00200000,
122 TxMxdma_32 = 0x00300000,
123 TxMxdma_64 = 0x00400000,
124 TxMxdma_128 = 0x00500000,
125 TxMxdma_256 = 0x00600000,
126 TxMxdma_512 = 0x00700000,
127 TxMxdma_1024 = 0x00000000,
128 TxCollRetry = 0x00800000,
129 TxAutoPad = 0x10000000,
130 TxMacLoop = 0x20000000,
131 TxHeartIgn = 0x40000000,
132 TxCarrierIgn = 0x80000000
133 };
134
135 enum RxConfig_bits {
136 RxDrthMask = 0x0000003e,
137 RxMxdmaMask = 0x00700000,
138 RxMxdma_8 = 0x00100000,
139 RxMxdma_16 = 0x00200000,
140 RxMxdma_32 = 0x00300000,
141 RxMxdma_64 = 0x00400000,
142 RxMxdma_128 = 0x00500000,
143 RxMxdma_256 = 0x00600000,
144 RxMxdma_512 = 0x00700000,
145 RxMxdma_1024 = 0x00000000,
146 RxAcceptLenErr = 0x04000000,
147 RxAcceptLong = 0x08000000,
148 RxAcceptTx = 0x10000000,
149 RxStripCRC = 0x20000000,
150 RxAcceptRunt = 0x40000000,
151 RxAcceptErr = 0x80000000,
152 };
153
154 /* Bits in the RxMode register. */
155 enum rx_mode_bits {
156 RxFilterEnable = 0x80000000,
157 AcceptAllBroadcast = 0x40000000,
158 AcceptAllMulticast = 0x20000000,
159 AcceptAllUnicast = 0x10000000,
160 AcceptPerfectMatch = 0x08000000,
161 };
162
163 typedef struct _BufferDesc {
164 u32 link;
165 u32 bufptr;
166 vu_long cmdsts;
167 u32 extsts; /*not used here */
168 } BufferDesc;
169
170 /* Bits in network_desc.status */
171 enum desc_status_bits {
172 DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
173 DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
174 DescSizeMask = 0xfff,
175
176 DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
177 DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
178 DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
179 DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
180
181 DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
182 DescRxDest = 0x01800000, DescRxLong = 0x00400000,
183 DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
184 DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
185 DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
186 };
187
188 /* Bits in MEAR */
189 enum mii_reg_bits {
190 MDIO_ShiftClk = 0x0040,
191 MDIO_EnbOutput = 0x0020,
192 MDIO_Data = 0x0010,
193 };
194
195 /* PHY Register offsets. */
196 enum phy_reg_offsets {
197 BMCR = 0x00,
198 BMSR = 0x01,
199 PHYIDR1 = 0x02,
200 PHYIDR2 = 0x03,
201 ANAR = 0x04,
202 KTCR = 0x09,
203 };
204
205 /* basic mode control register bits */
206 enum bmcr_bits {
207 Bmcr_Reset = 0x8000,
208 Bmcr_Loop = 0x4000,
209 Bmcr_Speed0 = 0x2000,
210 Bmcr_AutoNegEn = 0x1000, /*if set ignores Duplex, Speed[01] */
211 Bmcr_RstAutoNeg = 0x0200,
212 Bmcr_Duplex = 0x0100,
213 Bmcr_Speed1 = 0x0040,
214 Bmcr_Force10H = 0x0000,
215 Bmcr_Force10F = 0x0100,
216 Bmcr_Force100H = 0x2000,
217 Bmcr_Force100F = 0x2100,
218 Bmcr_Force1000H = 0x0040,
219 Bmcr_Force1000F = 0x0140,
220 };
221
222 /* auto negotiation advertisement register */
223 enum anar_bits {
224 anar_adv_100F = 0x0100,
225 anar_adv_100H = 0x0080,
226 anar_adv_10F = 0x0040,
227 anar_adv_10H = 0x0020,
228 anar_ieee_8023 = 0x0001,
229 };
230
231 /* 1K-base T control register */
232 enum ktcr_bits {
233 ktcr_adv_1000H = 0x0100,
234 ktcr_adv_1000F = 0x0200,
235 };
236
237 /* Globals */
238 static u32 SavedClkRun;
239 static unsigned int cur_rx;
240 static unsigned int rx_config;
241 static unsigned int tx_config;
242
243 /* Note: transmit and receive buffers and descriptors must be
244 long long word aligned */
245 static BufferDesc txd __attribute__ ((aligned(8)));
246 static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(8)));
247 static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(8)));
248 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
249 __attribute__ ((aligned(8)));
250
251 /* Function Prototypes */
252 static int mdio_read(struct eth_device *dev, int phy_id, int addr);
253 static void mdio_write(struct eth_device *dev, int phy_id, int addr, int value);
254 static void mdio_sync(struct eth_device *dev, u32 offset);
255 static int ns8382x_init(struct eth_device *dev, struct bd_info * bis);
256 static void ns8382x_reset(struct eth_device *dev);
257 static void ns8382x_init_rxfilter(struct eth_device *dev);
258 static void ns8382x_init_txd(struct eth_device *dev);
259 static void ns8382x_init_rxd(struct eth_device *dev);
260 static void ns8382x_set_rx_mode(struct eth_device *dev);
261 static void ns8382x_check_duplex(struct eth_device *dev);
262 static int ns8382x_send(struct eth_device *dev, void *packet, int length);
263 static int ns8382x_poll(struct eth_device *dev);
264 static void ns8382x_disable(struct eth_device *dev);
265
266 static struct pci_device_id supported[] = {
267 {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83820},
268 {}
269 };
270
271 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
272 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
273
274 static inline int
INW(struct eth_device * dev,u_long addr)275 INW(struct eth_device *dev, u_long addr)
276 {
277 return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
278 }
279
280 static int
INL(struct eth_device * dev,u_long addr)281 INL(struct eth_device *dev, u_long addr)
282 {
283 return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
284 }
285
286 static inline void
OUTW(struct eth_device * dev,int command,u_long addr)287 OUTW(struct eth_device *dev, int command, u_long addr)
288 {
289 *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
290 }
291
292 static inline void
OUTL(struct eth_device * dev,int command,u_long addr)293 OUTL(struct eth_device *dev, int command, u_long addr)
294 {
295 *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
296 }
297
298 /* Function: ns8382x_initialize
299 * Description: Retrieves the MAC address of the card, and sets up some
300 * globals required by other routines, and initializes the NIC, making it
301 * ready to send and receive packets.
302 * Side effects: initializes ns8382xs, ready to receive packets.
303 * Returns: int: number of cards found
304 */
305
306 int
ns8382x_initialize(struct bd_info * bis)307 ns8382x_initialize(struct bd_info * bis)
308 {
309 pci_dev_t devno;
310 int card_number = 0;
311 struct eth_device *dev;
312 u32 iobase, status;
313 int i, idx = 0;
314 u32 phyAddress;
315 u32 tmp;
316 u32 chip_config;
317
318 while (1) { /* Find PCI device(s) */
319 if ((devno = pci_find_devices(supported, idx++)) < 0)
320 break;
321
322 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
323 iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */
324
325 debug("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase);
326
327 pci_write_config_dword(devno, PCI_COMMAND,
328 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
329
330 /* Check if I/O accesses and Bus Mastering are enabled. */
331 pci_read_config_dword(devno, PCI_COMMAND, &status);
332 if (!(status & PCI_COMMAND_MEMORY)) {
333 printf("Error: Can not enable MEM access.\n");
334 continue;
335 } else if (!(status & PCI_COMMAND_MASTER)) {
336 printf("Error: Can not enable Bus Mastering.\n");
337 continue;
338 }
339
340 dev = (struct eth_device *) malloc(sizeof *dev);
341 if (!dev) {
342 printf("ns8382x: Can not allocate memory\n");
343 break;
344 }
345 memset(dev, 0, sizeof(*dev));
346
347 sprintf(dev->name, "dp8382x#%d", card_number);
348 dev->iobase = bus_to_phys(iobase);
349 dev->priv = (void *) devno;
350 dev->init = ns8382x_init;
351 dev->halt = ns8382x_disable;
352 dev->send = ns8382x_send;
353 dev->recv = ns8382x_poll;
354
355 /* ns8382x has a non-standard PM control register
356 * in PCI config space. Some boards apparently need
357 * to be brought to D0 in this manner. */
358 pci_read_config_dword(devno, PCIPM, &tmp);
359 if (tmp & (0x03 | 0x100)) { /* D0 state, disable PME assertion */
360 u32 newtmp = tmp & ~(0x03 | 0x100);
361 pci_write_config_dword(devno, PCIPM, newtmp);
362 }
363
364 /* get MAC address */
365 for (i = 0; i < 3; i++) {
366 u32 data;
367 char *mac = (char *)&dev->enetaddr[i * 2];
368
369 OUTL(dev, i * 2, RxFilterAddr);
370 data = INL(dev, RxFilterData);
371 *mac++ = data;
372 *mac++ = data >> 8;
373 }
374 /* get PHY address, can't be zero */
375 for (phyAddress = 1; phyAddress < 32; phyAddress++) {
376 u32 rev, phy1;
377
378 phy1 = mdio_read(dev, phyAddress, PHYIDR1);
379 if (phy1 == 0x2000) { /*check for 83861/91 */
380 rev = mdio_read(dev, phyAddress, PHYIDR2);
381 if ((rev & ~(0x000f)) == 0x00005c50 ||
382 (rev & ~(0x000f)) == 0x00005c60) {
383 debug("phy rev is %x\n", rev);
384 debug("phy address is %x\n",
385 phyAddress);
386 break;
387 }
388 }
389 }
390
391 /* set phy to autonegotiate && advertise everything */
392 mdio_write(dev, phyAddress, KTCR,
393 (ktcr_adv_1000H | ktcr_adv_1000F));
394 mdio_write(dev, phyAddress, ANAR,
395 (anar_adv_100F | anar_adv_100H | anar_adv_10H |
396 anar_adv_10F | anar_ieee_8023));
397 mdio_write(dev, phyAddress, BMCR, 0x0); /*restore */
398 mdio_write(dev, phyAddress, BMCR,
399 (Bmcr_AutoNegEn | Bmcr_RstAutoNeg));
400 /* Reset the chip to erase any previous misconfiguration. */
401 OUTL(dev, (ChipReset), ChipCmd);
402
403 chip_config = INL(dev, ChipConfig);
404 /* reset the phy */
405 OUTL(dev, (chip_config | PhyRst), ChipConfig);
406 /* power up and initialize transceiver */
407 OUTL(dev, (chip_config & ~(PhyDis)), ChipConfig);
408
409 mdio_sync(dev, EECtrl);
410
411 {
412 u32 chpcfg =
413 INL(dev, ChipConfig) ^ SpeedStatus_Polarity;
414
415 debug("%s: Transceiver 10%s %s duplex.\n", dev->name,
416 (chpcfg & GigSpeed) ? "00" : (chpcfg & HundSpeed)
417 ? "0" : "",
418 chpcfg & FullDuplex ? "full" : "half");
419 debug("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
420 dev->enetaddr[0], dev->enetaddr[1],
421 dev->enetaddr[2], dev->enetaddr[3],
422 dev->enetaddr[4], dev->enetaddr[5]);
423 }
424
425 /* Disable PME:
426 * The PME bit is initialized from the EEPROM contents.
427 * PCI cards probably have PME disabled, but motherboard
428 * implementations may have PME set to enable WakeOnLan.
429 * With PME set the chip will scan incoming packets but
430 * nothing will be written to memory. */
431 SavedClkRun = INL(dev, ClkRun);
432 OUTL(dev, SavedClkRun & ~0x100, ClkRun);
433
434 eth_register(dev);
435
436 card_number++;
437
438 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x60);
439
440 udelay(10 * 1000);
441 }
442 return card_number;
443 }
444
445 /* MII transceiver control section.
446 Read and write MII registers using software-generated serial MDIO
447 protocol. See the MII specifications or DP83840A data sheet for details.
448
449 The maximum data clock rate is 2.5 MHz. To meet minimum timing we
450 must flush writes to the PCI bus with a PCI read. */
451 #define mdio_delay(mdio_addr) INL(dev, mdio_addr)
452
453 #define MDIO_EnbIn (0)
454 #define MDIO_WRITE0 (MDIO_EnbOutput)
455 #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
456
457 /* Generate the preamble required for initial synchronization and
458 a few older transceivers. */
459 static void
mdio_sync(struct eth_device * dev,u32 offset)460 mdio_sync(struct eth_device *dev, u32 offset)
461 {
462 int bits = 32;
463
464 /* Establish sync by sending at least 32 logic ones. */
465 while (--bits >= 0) {
466 OUTL(dev, MDIO_WRITE1, offset);
467 mdio_delay(offset);
468 OUTL(dev, MDIO_WRITE1 | MDIO_ShiftClk, offset);
469 mdio_delay(offset);
470 }
471 }
472
473 static int
mdio_read(struct eth_device * dev,int phy_id,int addr)474 mdio_read(struct eth_device *dev, int phy_id, int addr)
475 {
476 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | addr;
477 int i, retval = 0;
478
479 /* Shift the read command bits out. */
480 for (i = 15; i >= 0; i--) {
481 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
482
483 OUTL(dev, dataval, EECtrl);
484 mdio_delay(EECtrl);
485 OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
486 mdio_delay(EECtrl);
487 }
488 /* Read the two transition, 16 data, and wire-idle bits. */
489 for (i = 19; i > 0; i--) {
490 OUTL(dev, MDIO_EnbIn, EECtrl);
491 mdio_delay(EECtrl);
492 retval =
493 (retval << 1) | ((INL(dev, EECtrl) & MDIO_Data) ? 1 : 0);
494 OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
495 mdio_delay(EECtrl);
496 }
497 return (retval >> 1) & 0xffff;
498 }
499
500 static void
mdio_write(struct eth_device * dev,int phy_id,int addr,int value)501 mdio_write(struct eth_device *dev, int phy_id, int addr, int value)
502 {
503 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (addr << 18) | value;
504 int i;
505
506 /* Shift the command bits out. */
507 for (i = 31; i >= 0; i--) {
508 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
509
510 OUTL(dev, dataval, EECtrl);
511 mdio_delay(EECtrl);
512 OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
513 mdio_delay(EECtrl);
514 }
515 /* Clear out extra bits. */
516 for (i = 2; i > 0; i--) {
517 OUTL(dev, MDIO_EnbIn, EECtrl);
518 mdio_delay(EECtrl);
519 OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
520 mdio_delay(EECtrl);
521 }
522 return;
523 }
524
525 /* Function: ns8382x_init
526 * Description: resets the ethernet controller chip and configures
527 * registers and data structures required for sending and receiving packets.
528 * Arguments: struct eth_device *dev: NIC data structure
529 * returns: int.
530 */
531
532 static int
ns8382x_init(struct eth_device * dev,struct bd_info * bis)533 ns8382x_init(struct eth_device *dev, struct bd_info * bis)
534 {
535 u32 config;
536
537 ns8382x_reset(dev);
538
539 /* Disable PME:
540 * The PME bit is initialized from the EEPROM contents.
541 * PCI cards probably have PME disabled, but motherboard
542 * implementations may have PME set to enable WakeOnLan.
543 * With PME set the chip will scan incoming packets but
544 * nothing will be written to memory. */
545 OUTL(dev, SavedClkRun & ~0x100, ClkRun);
546
547 ns8382x_init_rxfilter(dev);
548 ns8382x_init_txd(dev);
549 ns8382x_init_rxd(dev);
550
551 /*set up ChipConfig */
552 config = INL(dev, ChipConfig);
553 /*turn off 64 bit ops && Ten-bit interface
554 * && big-endian mode && extended status */
555 config &= ~(TBIEn | Mode1000 | T64En | D64En | M64En | BEMode | PhyDis | ExtStEn);
556 OUTL(dev, config, ChipConfig);
557
558 /* Configure the PCI bus bursts and FIFO thresholds. */
559 tx_config = TxCarrierIgn | TxHeartIgn | TxAutoPad
560 | TxCollRetry | TxMxdma_1024 | (0x1002);
561 rx_config = RxMxdma_1024 | 0x20;
562
563 debug("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
564 debug("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
565
566 OUTL(dev, tx_config, TxConfig);
567 OUTL(dev, rx_config, RxConfig);
568
569 /*turn off priority queueing */
570 OUTL(dev, 0x0, PriQueue);
571
572 ns8382x_check_duplex(dev);
573 ns8382x_set_rx_mode(dev);
574
575 OUTL(dev, (RxOn | TxOn), ChipCmd);
576 return 1;
577 }
578
579 /* Function: ns8382x_reset
580 * Description: soft resets the controller chip
581 * Arguments: struct eth_device *dev: NIC data structure
582 * Returns: void.
583 */
584 static void
ns8382x_reset(struct eth_device * dev)585 ns8382x_reset(struct eth_device *dev)
586 {
587 OUTL(dev, ChipReset, ChipCmd);
588 while (INL(dev, ChipCmd))
589 /*wait until done */ ;
590 OUTL(dev, 0, IntrMask);
591 OUTL(dev, 0, IntrEnable);
592 }
593
594 /* Function: ns8382x_init_rxfilter
595 * Description: sets receive filter address to our MAC address
596 * Arguments: struct eth_device *dev: NIC data structure
597 * returns: void.
598 */
599
600 static void
ns8382x_init_rxfilter(struct eth_device * dev)601 ns8382x_init_rxfilter(struct eth_device *dev)
602 {
603 int i;
604
605 for (i = 0; i < ETH_ALEN; i += 2) {
606 OUTL(dev, i, RxFilterAddr);
607 OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
608 RxFilterData);
609 }
610 }
611
612 /* Function: ns8382x_init_txd
613 * Description: initializes the Tx descriptor
614 * Arguments: struct eth_device *dev: NIC data structure
615 * returns: void.
616 */
617
618 static void
ns8382x_init_txd(struct eth_device * dev)619 ns8382x_init_txd(struct eth_device *dev)
620 {
621 txd.link = (u32) 0;
622 txd.bufptr = cpu_to_le32((u32) & txb[0]);
623 txd.cmdsts = (u32) 0;
624 txd.extsts = (u32) 0;
625
626 OUTL(dev, 0x0, TxRingPtrHi);
627 OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr);
628
629 debug("ns8382x_init_txd: TX descriptor register loaded with: %#08X (&txd: %p)\n",
630 INL(dev, TxRingPtr), &txd);
631 }
632
633 /* Function: ns8382x_init_rxd
634 * Description: initializes the Rx descriptor ring
635 * Arguments: struct eth_device *dev: NIC data structure
636 * Returns: void.
637 */
638
639 static void
ns8382x_init_rxd(struct eth_device * dev)640 ns8382x_init_rxd(struct eth_device *dev)
641 {
642 int i;
643
644 OUTL(dev, 0x0, RxRingPtrHi);
645
646 cur_rx = 0;
647 for (i = 0; i < NUM_RX_DESC; i++) {
648 rxd[i].link =
649 cpu_to_le32((i + 1 <
650 NUM_RX_DESC) ? (u32) & rxd[i +
651 1] : (u32) &
652 rxd[0]);
653 rxd[i].extsts = cpu_to_le32((u32) 0x0);
654 rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
655 rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
656
657 debug
658 ("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n",
659 i, &rxd[i], le32_to_cpu(rxd[i].link),
660 le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr));
661 }
662 OUTL(dev, phys_to_bus((u32) & rxd), RxRingPtr);
663
664 debug("ns8382x_init_rxd: RX descriptor register loaded with: %X\n",
665 INL(dev, RxRingPtr));
666 }
667
668 /* Function: ns8382x_set_rx_mode
669 * Description:
670 * sets the receive mode to accept all broadcast packets and packets
671 * with our MAC address, and reject all multicast packets.
672 * Arguments: struct eth_device *dev: NIC data structure
673 * Returns: void.
674 */
675
676 static void
ns8382x_set_rx_mode(struct eth_device * dev)677 ns8382x_set_rx_mode(struct eth_device *dev)
678 {
679 u32 rx_mode = 0x0;
680 /*spec says RxFilterEnable has to be 0 for rest of
681 * this stuff to be properly configured. Linux driver
682 * seems to support this*/
683 /* OUTL(dev, rx_mode, RxFilterAddr);*/
684 rx_mode = (RxFilterEnable | AcceptAllBroadcast | AcceptPerfectMatch);
685 OUTL(dev, rx_mode, RxFilterAddr);
686 printf("ns8382x_set_rx_mode: set to %X\n", rx_mode);
687 /*now we turn RxFilterEnable back on */
688 /*rx_mode |= RxFilterEnable;
689 OUTL(dev, rx_mode, RxFilterAddr);*/
690 }
691
692 static void
ns8382x_check_duplex(struct eth_device * dev)693 ns8382x_check_duplex(struct eth_device *dev)
694 {
695 int gig = 0;
696 int hun = 0;
697 int duplex = 0;
698 int config = (INL(dev, ChipConfig) ^ SpeedStatus_Polarity);
699
700 duplex = (config & FullDuplex) ? 1 : 0;
701 gig = (config & GigSpeed) ? 1 : 0;
702 hun = (config & HundSpeed) ? 1 : 0;
703
704 debug("%s: Setting 10%s %s-duplex based on negotiated link"
705 " capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "",
706 duplex ? "full" : "half");
707
708 if (duplex) {
709 rx_config |= RxAcceptTx;
710 tx_config |= (TxCarrierIgn | TxHeartIgn);
711 } else {
712 rx_config &= ~RxAcceptTx;
713 tx_config &= ~(TxCarrierIgn | TxHeartIgn);
714 }
715
716 debug("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config);
717 debug("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config);
718
719 OUTL(dev, tx_config, TxConfig);
720 OUTL(dev, rx_config, RxConfig);
721
722 /*if speed is 10 or 100, remove MODE1000,
723 * if it's 1000, then set it */
724 config = INL(dev, ChipConfig);
725 if (gig)
726 config |= Mode1000;
727 else
728 config &= ~Mode1000;
729
730 debug("%s: %setting Mode1000\n", dev->name, (gig) ? "S" : "Uns");
731
732 OUTL(dev, config, ChipConfig);
733 }
734
735 /* Function: ns8382x_send
736 * Description: transmits a packet and waits for completion or timeout.
737 * Returns: void. */
ns8382x_send(struct eth_device * dev,void * packet,int length)738 static int ns8382x_send(struct eth_device *dev, void *packet, int length)
739 {
740 u32 i, status = 0;
741 vu_long tx_stat = 0;
742
743 /* Stop the transmitter */
744 OUTL(dev, TxOff, ChipCmd);
745
746 debug("ns8382x_send: sending %d bytes\n", (int)length);
747
748 /* set the transmit buffer descriptor and enable Transmit State Machine */
749 txd.link = cpu_to_le32(0x0);
750 txd.bufptr = cpu_to_le32(phys_to_bus((u32)packet));
751 txd.extsts = cpu_to_le32(0x0);
752 txd.cmdsts = cpu_to_le32(DescOwn | length);
753
754 /* load Transmit Descriptor Register */
755 OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
756
757 debug("ns8382x_send: TX descriptor register loaded with: %#08X\n",
758 INL(dev, TxRingPtr));
759 debug("\ttxd.link:%X\tbufp:%X\texsts:%X\tcmdsts:%X\n",
760 le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr),
761 le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts));
762
763 /* restart the transmitter */
764 OUTL(dev, TxOn, ChipCmd);
765
766 for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
767 if (i >= TOUT_LOOP) {
768 printf ("%s: tx error buffer not ready: txd.cmdsts %#lX\n",
769 dev->name, tx_stat);
770 goto Done;
771 }
772 }
773
774 if (!(tx_stat & DescPktOK)) {
775 printf("ns8382x_send: Transmit error, Tx status %lX.\n", tx_stat);
776 goto Done;
777 }
778
779 debug("ns8382x_send: tx_stat: %#08lX\n", tx_stat);
780
781 status = 1;
782 Done:
783 return status;
784 }
785
786 /* Function: ns8382x_poll
787 * Description: checks for a received packet and returns it if found.
788 * Arguments: struct eth_device *dev: NIC data structure
789 * Returns: 1 if packet was received.
790 * 0 if no packet was received.
791 * Side effects:
792 * Returns (copies) the packet to the array dev->packet.
793 * Returns the length of the packet.
794 */
795
796 static int
ns8382x_poll(struct eth_device * dev)797 ns8382x_poll(struct eth_device *dev)
798 {
799 int retstat = 0;
800 int length = 0;
801 vu_long rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
802
803 if (!(rx_status & (u32) DescOwn))
804 return retstat;
805
806 debug("ns8382x_poll: got a packet: cur_rx:%u, status:%lx\n",
807 cur_rx, rx_status);
808
809 length = (rx_status & DSIZE) - CRC_SIZE;
810
811 if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
812 /* corrupted packet received */
813 printf("ns8382x_poll: Corrupted packet, status:%lx\n",
814 rx_status);
815 retstat = 0;
816 } else {
817 /* give packet to higher level routine */
818 net_process_received_packet((rxb + cur_rx * RX_BUF_SIZE),
819 length);
820 retstat = 1;
821 }
822
823 /* return the descriptor and buffer to receive ring */
824 rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
825 rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
826
827 if (++cur_rx == NUM_RX_DESC)
828 cur_rx = 0;
829
830 /* re-enable the potentially idle receive state machine */
831 OUTL(dev, RxOn, ChipCmd);
832
833 return retstat;
834 }
835
836 /* Function: ns8382x_disable
837 * Description: Turns off interrupts and stops Tx and Rx engines
838 * Arguments: struct eth_device *dev: NIC data structure
839 * Returns: void.
840 */
841
842 static void
ns8382x_disable(struct eth_device * dev)843 ns8382x_disable(struct eth_device *dev)
844 {
845 /* Disable interrupts using the mask. */
846 OUTL(dev, 0, IntrMask);
847 OUTL(dev, 0, IntrEnable);
848
849 /* Stop the chip's Tx and Rx processes. */
850 OUTL(dev, (RxOff | TxOff), ChipCmd);
851
852 /* Restore PME enable bit */
853 OUTL(dev, SavedClkRun, ClkRun);
854 }
855