1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Aquantia PHY drivers
4 *
5 * Copyright 2014 Freescale Semiconductor, Inc.
6 * Copyright 2018 NXP
7 */
8 #include <config.h>
9 #include <common.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <net.h>
13 #include <phy.h>
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
16 #include <u-boot/crc.h>
17 #include <malloc.h>
18 #include <asm/byteorder.h>
19 #include <fs.h>
20
21 #define AQUNTIA_10G_CTL 0x20
22 #define AQUNTIA_VENDOR_P1 0xc400
23
24 #define AQUNTIA_SPEED_LSB_MASK 0x2000
25 #define AQUNTIA_SPEED_MSB_MASK 0x40
26
27 #define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812
28 #define AQUANTIA_SYSTEM_INTERFACE_SR_READY BIT(0)
29 #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
30 #define AQUANTIA_FIRMWARE_ID 0x20
31 #define AQUANTIA_RESERVED_STATUS 0xc885
32 #define AQUANTIA_FIRMWARE_MAJOR_MASK 0xff00
33 #define AQUANTIA_FIRMWARE_MINOR_MASK 0xff
34 #define AQUANTIA_FIRMWARE_BUILD_MASK 0xf0
35
36 #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
37 #define AQUANTIA_SI_IN_USE_MASK 0x0078
38 #define AQUANTIA_SI_USXGMII 0x0018
39
40 /* registers in MDIO_MMD_VEND1 region */
41 #define AQUANTIA_VND1_GLOBAL_SC 0x000
42 #define AQUANTIA_VND1_GLOBAL_SC_LP BIT(0xb)
43
44 #define GLOBAL_FIRMWARE_ID 0x20
45 #define GLOBAL_FAULT 0xc850
46 #define GLOBAL_RSTATUS_1 0xc885
47
48 #define GLOBAL_ALARM_1 0xcc00
49 #define SYSTEM_READY_BIT 0x40
50
51 #define GLOBAL_STANDARD_CONTROL 0x0
52 #define SOFT_RESET BIT(15)
53 #define LOW_POWER BIT(11)
54
55 #define MAILBOX_CONTROL 0x0200
56 #define MAILBOX_EXECUTE BIT(15)
57 #define MAILBOX_WRITE BIT(14)
58 #define MAILBOX_RESET_CRC BIT(12)
59 #define MAILBOX_BUSY BIT(8)
60
61 #define MAILBOX_CRC 0x0201
62
63 #define MAILBOX_ADDR_MSW 0x0202
64 #define MAILBOX_ADDR_LSW 0x0203
65
66 #define MAILBOX_DATA_MSW 0x0204
67 #define MAILBOX_DATA_LSW 0x0205
68
69 #define UP_CONTROL 0xc001
70 #define UP_RESET BIT(15)
71 #define UP_RUN_STALL_OVERRIDE BIT(6)
72 #define UP_RUN_STALL BIT(0)
73
74 #define AQUANTIA_PMA_RX_VENDOR_P1 0xe400
75 #define AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK GENMASK(1, 0)
76 /* MDI reversal configured through registers */
77 #define AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG BIT(1)
78 /* MDI reversal enabled */
79 #define AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV BIT(0)
80
81 /*
82 * global start rate, the protocol associated with this speed is used by default
83 * on SI.
84 */
85 #define AQUANTIA_VND1_GSTART_RATE 0x31a
86 #define AQUANTIA_VND1_GSTART_RATE_OFF 0
87 #define AQUANTIA_VND1_GSTART_RATE_100M 1
88 #define AQUANTIA_VND1_GSTART_RATE_1G 2
89 #define AQUANTIA_VND1_GSTART_RATE_10G 3
90 #define AQUANTIA_VND1_GSTART_RATE_2_5G 4
91 #define AQUANTIA_VND1_GSTART_RATE_5G 5
92
93 /* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
94 #define AQUANTIA_VND1_GSYSCFG_BASE 0x31b
95 #define AQUANTIA_VND1_GSYSCFG_100M 0
96 #define AQUANTIA_VND1_GSYSCFG_1G 1
97 #define AQUANTIA_VND1_GSYSCFG_2_5G 2
98 #define AQUANTIA_VND1_GSYSCFG_5G 3
99 #define AQUANTIA_VND1_GSYSCFG_10G 4
100
101 #define AQUANTIA_VND1_SMBUS0 0xc485
102 #define AQUANTIA_VND1_SMBUS1 0xc495
103
104 /* addresses of memory segments in the phy */
105 #define DRAM_BASE_ADDR 0x3FFE0000
106 #define IRAM_BASE_ADDR 0x40000000
107
108 /* firmware image format constants */
109 #define VERSION_STRING_SIZE 0x40
110 #define VERSION_STRING_OFFSET 0x0200
111 #define HEADER_OFFSET 0x300
112
113 /* driver private data */
114 #define AQUANTIA_NA 0
115 #define AQUANTIA_GEN1 1
116 #define AQUANTIA_GEN2 2
117 #define AQUANTIA_GEN3 3
118
119 #pragma pack(1)
120 struct fw_header {
121 u8 padding[4];
122 u8 iram_offset[3];
123 u8 iram_size[3];
124 u8 dram_offset[3];
125 u8 dram_size[3];
126 };
127
128 #pragma pack()
129
130 #if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW)
aquantia_read_fw(u8 ** fw_addr,size_t * fw_length)131 static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
132 {
133 loff_t length, read;
134 int ret;
135 void *addr = NULL;
136
137 *fw_addr = NULL;
138 *fw_length = 0;
139 debug("Loading Acquantia microcode from %s %s\n",
140 CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME);
141 ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
142 if (ret < 0)
143 goto cleanup;
144
145 ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length);
146 if (ret < 0)
147 goto cleanup;
148
149 addr = malloc(length);
150 if (!addr) {
151 ret = -ENOMEM;
152 goto cleanup;
153 }
154
155 ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
156 if (ret < 0)
157 goto cleanup;
158
159 ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,
160 &read);
161 if (ret < 0)
162 goto cleanup;
163
164 *fw_addr = addr;
165 *fw_length = length;
166 debug("Found Acquantia microcode.\n");
167
168 cleanup:
169 if (ret < 0) {
170 printf("loading firmware file %s %s failed with error %d\n",
171 CONFIG_PHY_AQUANTIA_FW_PART,
172 CONFIG_PHY_AQUANTIA_FW_NAME, ret);
173 free(addr);
174 }
175 return ret;
176 }
177
178 /* load data into the phy's memory */
aquantia_load_memory(struct phy_device * phydev,u32 addr,const u8 * data,size_t len)179 static int aquantia_load_memory(struct phy_device *phydev, u32 addr,
180 const u8 *data, size_t len)
181 {
182 size_t pos;
183 u16 crc = 0, up_crc;
184
185 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC);
186 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16);
187 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);
188
189 for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {
190 u32 word = 0;
191
192 memcpy(&word, &data[pos], min(sizeof(u32), len - pos));
193
194 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW,
195 (word >> 16));
196 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW,
197 word & 0xffff);
198
199 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL,
200 MAILBOX_EXECUTE | MAILBOX_WRITE);
201
202 /* keep a big endian CRC to match the phy processor */
203 word = cpu_to_be32(word);
204 crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word));
205 }
206
207 up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC);
208 if (crc != up_crc) {
209 printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",
210 phydev->dev->name, crc, up_crc);
211 return -EINVAL;
212 }
213 return 0;
214 }
215
unpack_u24(const u8 * data)216 static u32 unpack_u24(const u8 *data)
217 {
218 return (data[2] << 16) + (data[1] << 8) + data[0];
219 }
220
aquantia_upload_firmware(struct phy_device * phydev)221 static int aquantia_upload_firmware(struct phy_device *phydev)
222 {
223 int ret;
224 u8 *addr = NULL;
225 size_t fw_length = 0;
226 u16 calculated_crc, read_crc;
227 char version[VERSION_STRING_SIZE];
228 u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size;
229 const struct fw_header *header;
230
231 ret = aquantia_read_fw(&addr, &fw_length);
232 if (ret != 0)
233 return ret;
234
235 read_crc = (addr[fw_length - 2] << 8) | addr[fw_length - 1];
236 calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
237 if (read_crc != calculated_crc) {
238 printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
239 phydev->dev->name, read_crc, calculated_crc);
240 ret = -EINVAL;
241 goto done;
242 }
243
244 /* Find the DRAM and IRAM sections within the firmware file. */
245 primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;
246
247 header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET];
248
249 iram_offset = primary_offset + unpack_u24(header->iram_offset);
250 iram_size = unpack_u24(header->iram_size);
251
252 dram_offset = primary_offset + unpack_u24(header->dram_offset);
253 dram_size = unpack_u24(header->dram_size);
254
255 debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n",
256 primary_offset, iram_offset, iram_size, dram_offset, dram_size);
257
258 strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
259 VERSION_STRING_SIZE);
260 printf("%s loading firmare version '%s'\n", phydev->dev->name, version);
261
262 /* stall the microcprocessor */
263 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
264 UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
265
266 debug("loading dram 0x%08x from offset=%d size=%d\n",
267 DRAM_BASE_ADDR, dram_offset, dram_size);
268 ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
269 dram_size);
270 if (ret != 0)
271 goto done;
272
273 debug("loading iram 0x%08x from offset=%d size=%d\n",
274 IRAM_BASE_ADDR, iram_offset, iram_size);
275 ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
276 iram_size);
277 if (ret != 0)
278 goto done;
279
280 /* make sure soft reset and low power mode are clear */
281 phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);
282
283 /* Release the microprocessor. UP_RESET must be held for 100 usec. */
284 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
285 UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET);
286
287 udelay(100);
288
289 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE);
290
291 printf("%s firmare loading done.\n", phydev->dev->name);
292 done:
293 free(addr);
294 return ret;
295 }
296 #else
aquantia_upload_firmware(struct phy_device * phydev)297 static int aquantia_upload_firmware(struct phy_device *phydev)
298 {
299 printf("ERROR %s firmware loading disabled.\n", phydev->dev->name);
300 return -1;
301 }
302 #endif
303
304 struct {
305 u16 syscfg;
306 int cnt;
307 u16 start_rate;
308 } aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = {
309 [PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
310 AQUANTIA_VND1_GSTART_RATE_1G},
311 [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
312 AQUANTIA_VND1_GSTART_RATE_2_5G},
313 [PHY_INTERFACE_MODE_XFI] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
314 AQUANTIA_VND1_GSTART_RATE_10G},
315 [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G,
316 AQUANTIA_VND1_GSTART_RATE_10G},
317 };
318
aquantia_set_proto(struct phy_device * phydev,phy_interface_t interface)319 static int aquantia_set_proto(struct phy_device *phydev,
320 phy_interface_t interface)
321 {
322 int i;
323
324 if (!aquantia_syscfg[interface].cnt)
325 return 0;
326
327 /* set the default rate to enable the SI link */
328 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
329 aquantia_syscfg[interface].start_rate);
330
331 /* set selected protocol for all relevant line side link speeds */
332 for (i = 0; i <= aquantia_syscfg[interface].cnt; i++)
333 phy_write(phydev, MDIO_MMD_VEND1,
334 AQUANTIA_VND1_GSYSCFG_BASE + i,
335 aquantia_syscfg[interface].syscfg);
336 return 0;
337 }
338
aquantia_dts_config(struct phy_device * phydev)339 static int aquantia_dts_config(struct phy_device *phydev)
340 {
341 #ifdef CONFIG_DM_ETH
342 ofnode node = phydev->node;
343 u32 prop;
344 u16 reg;
345
346 /* this code only works on gen2 and gen3 PHYs */
347 if (phydev->drv->data != AQUANTIA_GEN2 &&
348 phydev->drv->data != AQUANTIA_GEN3)
349 return -ENOTSUPP;
350
351 if (!ofnode_valid(node))
352 return 0;
353
354 if (!ofnode_read_u32(node, "mdi-reversal", &prop)) {
355 debug("mdi-reversal = %d\n", (int)prop);
356 reg = phy_read(phydev, MDIO_MMD_PMAPMD,
357 AQUANTIA_PMA_RX_VENDOR_P1);
358 reg &= ~AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK;
359 reg |= AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG;
360 reg |= prop ? AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV : 0;
361 phy_write(phydev, MDIO_MMD_PMAPMD, AQUANTIA_PMA_RX_VENDOR_P1,
362 reg);
363 }
364 if (!ofnode_read_u32(node, "smb-addr", &prop)) {
365 debug("smb-addr = %x\n", (int)prop);
366 /*
367 * there are two addresses here, normally just one bus would
368 * be in use so we're setting both regs using the same DT
369 * property.
370 */
371 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS0,
372 (u16)(prop << 1));
373 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS1,
374 (u16)(prop << 1));
375 }
376
377 #endif
378 return 0;
379 }
380
aquantia_link_is_up(struct phy_device * phydev)381 static bool aquantia_link_is_up(struct phy_device *phydev)
382 {
383 u16 reg, regmask;
384 int devad, regnum;
385
386 /*
387 * On Gen 2 and 3 we have a bit that indicates that both system and
388 * line side are ready for data, use that if possible.
389 */
390 if (phydev->drv->data == AQUANTIA_GEN2 ||
391 phydev->drv->data == AQUANTIA_GEN3) {
392 devad = MDIO_MMD_PHYXS;
393 regnum = AQUANTIA_SYSTEM_INTERFACE_SR;
394 regmask = AQUANTIA_SYSTEM_INTERFACE_SR_READY;
395 } else {
396 devad = MDIO_MMD_AN;
397 regnum = MDIO_STAT1;
398 regmask = MDIO_AN_STAT1_COMPLETE;
399 }
400 /* the register should be latched, do a double read */
401 phy_read(phydev, devad, regnum);
402 reg = phy_read(phydev, devad, regnum);
403
404 return !!(reg & regmask);
405 }
406
aquantia_config(struct phy_device * phydev)407 int aquantia_config(struct phy_device *phydev)
408 {
409 int interface = phydev->interface;
410 u32 val, id, rstatus, fault;
411 u32 reg_val1 = 0;
412 int num_retries = 5;
413 int usx_an = 0;
414
415 /*
416 * check if the system is out of reset and init sequence completed.
417 * chip-wide reset for gen1 quad phys takes longer
418 */
419 while (--num_retries) {
420 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1);
421 if (rstatus & SYSTEM_READY_BIT)
422 break;
423 mdelay(10);
424 }
425
426 id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
427 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
428 fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT);
429
430 if (id != 0)
431 debug("%s running firmware version %X.%X.%X\n",
432 phydev->dev->name, (id >> 8), id & 0xff,
433 (rstatus >> 4) & 0xf);
434
435 if (fault != 0)
436 printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);
437
438 if (id == 0 || fault != 0) {
439 int ret;
440
441 ret = aquantia_upload_firmware(phydev);
442 if (ret != 0)
443 return ret;
444 }
445 /*
446 * for backward compatibility convert XGMII into either XFI or USX based
447 * on FW config
448 */
449 if (interface == PHY_INTERFACE_MODE_XGMII) {
450 debug("use XFI or USXGMII SI protos, XGMII is not valid\n");
451
452 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
453 AQUANTIA_SYSTEM_INTERFACE_SR);
454 if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
455 interface = PHY_INTERFACE_MODE_USXGMII;
456 else
457 interface = PHY_INTERFACE_MODE_XFI;
458 }
459
460 /*
461 * if link is up already we can just use it, otherwise configure
462 * the protocols in the PHY. If link is down set the system
463 * interface protocol to use based on phydev->interface
464 */
465 if (!aquantia_link_is_up(phydev) &&
466 (phydev->drv->data == AQUANTIA_GEN2 ||
467 phydev->drv->data == AQUANTIA_GEN3)) {
468 /* set PHY in low power mode so we can configure protocols */
469 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,
470 AQUANTIA_VND1_GLOBAL_SC_LP);
471 mdelay(10);
472
473 /* configure protocol based on phydev->interface */
474 aquantia_set_proto(phydev, interface);
475 /* apply custom configuration based on DT */
476 aquantia_dts_config(phydev);
477
478 /* wake PHY back up */
479 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
480 mdelay(10);
481 }
482
483 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
484
485 switch (interface) {
486 case PHY_INTERFACE_MODE_SGMII:
487 /* 1000BASE-T mode */
488 phydev->advertising = SUPPORTED_1000baseT_Full;
489 phydev->supported = phydev->advertising;
490
491 val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
492 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
493 break;
494 case PHY_INTERFACE_MODE_USXGMII:
495 usx_an = 1;
496 /* FALLTHROUGH */
497 case PHY_INTERFACE_MODE_XFI:
498 /* 10GBASE-T mode */
499 phydev->advertising = SUPPORTED_10000baseT_Full;
500 phydev->supported = phydev->advertising;
501
502 if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
503 !(val & AQUNTIA_SPEED_MSB_MASK))
504 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
505 AQUNTIA_SPEED_LSB_MASK |
506 AQUNTIA_SPEED_MSB_MASK);
507
508 /* If SI is USXGMII then start USXGMII autoneg */
509 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
510 AQUANTIA_VENDOR_PROVISIONING_REG);
511
512 if (usx_an) {
513 reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
514 debug("%s: system interface USXGMII\n",
515 phydev->dev->name);
516 } else {
517 reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
518 debug("%s: system interface XFI\n",
519 phydev->dev->name);
520 }
521
522 phy_write(phydev, MDIO_MMD_PHYXS,
523 AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
524 break;
525 case PHY_INTERFACE_MODE_SGMII_2500:
526 /* 2.5GBASE-T mode */
527 phydev->advertising = SUPPORTED_1000baseT_Full;
528 phydev->supported = phydev->advertising;
529
530 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
531 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
532 break;
533 case PHY_INTERFACE_MODE_MII:
534 /* 100BASE-TX mode */
535 phydev->advertising = SUPPORTED_100baseT_Full;
536 phydev->supported = phydev->advertising;
537
538 val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
539 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
540 break;
541 };
542
543 val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
544 reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
545
546 debug("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
547 phydev->drv->name,
548 (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
549 reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
550 (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
551
552 return 0;
553 }
554
aquantia_startup(struct phy_device * phydev)555 int aquantia_startup(struct phy_device *phydev)
556 {
557 u32 reg, speed;
558 int i = 0;
559
560 phydev->duplex = DUPLEX_FULL;
561
562 /* if the AN is still in progress, wait till timeout. */
563 if (!aquantia_link_is_up(phydev)) {
564 printf("%s Waiting for PHY auto negotiation to complete",
565 phydev->dev->name);
566 do {
567 udelay(1000);
568 if ((i++ % 500) == 0)
569 printf(".");
570 } while (!aquantia_link_is_up(phydev) &&
571 i < (4 * PHY_ANEG_TIMEOUT));
572
573 if (i > PHY_ANEG_TIMEOUT)
574 printf(" TIMEOUT !\n");
575 }
576
577 /* Read twice because link state is latched and a
578 * read moves the current state into the register */
579 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
580 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
581 if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
582 phydev->link = 0;
583 else
584 phydev->link = 1;
585
586 speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
587 if (speed & AQUNTIA_SPEED_MSB_MASK) {
588 if (speed & AQUNTIA_SPEED_LSB_MASK)
589 phydev->speed = SPEED_10000;
590 else
591 phydev->speed = SPEED_1000;
592 } else {
593 if (speed & AQUNTIA_SPEED_LSB_MASK)
594 phydev->speed = SPEED_100;
595 else
596 phydev->speed = SPEED_10;
597 }
598
599 return 0;
600 }
601
602 struct phy_driver aq1202_driver = {
603 .name = "Aquantia AQ1202",
604 .uid = 0x3a1b445,
605 .mask = 0xfffffff0,
606 .features = PHY_10G_FEATURES,
607 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
608 MDIO_MMD_PHYXS | MDIO_MMD_AN |
609 MDIO_MMD_VEND1),
610 .config = &aquantia_config,
611 .startup = &aquantia_startup,
612 .shutdown = &gen10g_shutdown,
613 };
614
615 struct phy_driver aq2104_driver = {
616 .name = "Aquantia AQ2104",
617 .uid = 0x3a1b460,
618 .mask = 0xfffffff0,
619 .features = PHY_10G_FEATURES,
620 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
621 MDIO_MMD_PHYXS | MDIO_MMD_AN |
622 MDIO_MMD_VEND1),
623 .config = &aquantia_config,
624 .startup = &aquantia_startup,
625 .shutdown = &gen10g_shutdown,
626 };
627
628 struct phy_driver aqr105_driver = {
629 .name = "Aquantia AQR105",
630 .uid = 0x3a1b4a2,
631 .mask = 0xfffffff0,
632 .features = PHY_10G_FEATURES,
633 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
634 MDIO_MMD_PHYXS | MDIO_MMD_AN |
635 MDIO_MMD_VEND1),
636 .config = &aquantia_config,
637 .startup = &aquantia_startup,
638 .shutdown = &gen10g_shutdown,
639 .data = AQUANTIA_GEN1,
640 };
641
642 struct phy_driver aqr106_driver = {
643 .name = "Aquantia AQR106",
644 .uid = 0x3a1b4d0,
645 .mask = 0xfffffff0,
646 .features = PHY_10G_FEATURES,
647 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
648 MDIO_MMD_PHYXS | MDIO_MMD_AN |
649 MDIO_MMD_VEND1),
650 .config = &aquantia_config,
651 .startup = &aquantia_startup,
652 .shutdown = &gen10g_shutdown,
653 };
654
655 struct phy_driver aqr107_driver = {
656 .name = "Aquantia AQR107",
657 .uid = 0x3a1b4e0,
658 .mask = 0xfffffff0,
659 .features = PHY_10G_FEATURES,
660 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
661 MDIO_MMD_PHYXS | MDIO_MMD_AN |
662 MDIO_MMD_VEND1),
663 .config = &aquantia_config,
664 .startup = &aquantia_startup,
665 .shutdown = &gen10g_shutdown,
666 .data = AQUANTIA_GEN2,
667 };
668
669 struct phy_driver aqr112_driver = {
670 .name = "Aquantia AQR112",
671 .uid = 0x3a1b660,
672 .mask = 0xfffffff0,
673 .features = PHY_10G_FEATURES,
674 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
675 MDIO_MMD_PHYXS | MDIO_MMD_AN |
676 MDIO_MMD_VEND1),
677 .config = &aquantia_config,
678 .startup = &aquantia_startup,
679 .shutdown = &gen10g_shutdown,
680 .data = AQUANTIA_GEN3,
681 };
682
683 struct phy_driver aqr113c_driver = {
684 .name = "Aquantia AQR113C",
685 .uid = 0x31c31c12,
686 .mask = 0xfffffff0,
687 .features = PHY_10G_FEATURES,
688 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
689 MDIO_MMD_PHYXS | MDIO_MMD_AN |
690 MDIO_MMD_VEND1),
691 .config = &aquantia_config,
692 .startup = &aquantia_startup,
693 .shutdown = &gen10g_shutdown,
694 .data = AQUANTIA_GEN3,
695 };
696
697 struct phy_driver aqr405_driver = {
698 .name = "Aquantia AQR405",
699 .uid = 0x3a1b4b2,
700 .mask = 0xfffffff0,
701 .features = PHY_10G_FEATURES,
702 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
703 MDIO_MMD_PHYXS | MDIO_MMD_AN |
704 MDIO_MMD_VEND1),
705 .config = &aquantia_config,
706 .startup = &aquantia_startup,
707 .shutdown = &gen10g_shutdown,
708 .data = AQUANTIA_GEN1,
709 };
710
711 struct phy_driver aqr412_driver = {
712 .name = "Aquantia AQR412",
713 .uid = 0x3a1b710,
714 .mask = 0xfffffff0,
715 .features = PHY_10G_FEATURES,
716 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
717 MDIO_MMD_PHYXS | MDIO_MMD_AN |
718 MDIO_MMD_VEND1),
719 .config = &aquantia_config,
720 .startup = &aquantia_startup,
721 .shutdown = &gen10g_shutdown,
722 .data = AQUANTIA_GEN3,
723 };
724
phy_aquantia_init(void)725 int phy_aquantia_init(void)
726 {
727 phy_register(&aq1202_driver);
728 phy_register(&aq2104_driver);
729 phy_register(&aqr105_driver);
730 phy_register(&aqr106_driver);
731 phy_register(&aqr107_driver);
732 phy_register(&aqr112_driver);
733 phy_register(&aqr113c_driver);
734 phy_register(&aqr405_driver);
735 phy_register(&aqr412_driver);
736
737 return 0;
738 }
739