1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * rtl8139.c : U-Boot driver for the RealTek RTL8139
4 *
5 * Masami Komiya (mkomiya@sonare.it)
6 *
7 * Most part is taken from rtl8139.c of etherboot
8 *
9 */
10
11 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
12 *
13 * ported from the linux driver written by Donald Becker
14 * by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
15 *
16 * changes to the original driver:
17 * - removed support for interrupts, switching to polling mode (yuck!)
18 * - removed support for the 8129 chip (external MII)
19 */
20
21 /*********************************************************************/
22 /* Revision History */
23 /*********************************************************************/
24
25 /*
26 * 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
27 * Put in virt_to_bus calls to allow Etherboot relocation.
28 *
29 * 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
30 * Following email from Hyun-Joon Cha, added a disable routine, otherwise
31 * NIC remains live and can crash the kernel later.
32 *
33 * 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
34 * Shuffled things around, removed the leftovers from the 8129 support
35 * that was in the Linux driver and added a bit more 8139 definitions.
36 * Moved the 8K receive buffer to a fixed, available address outside the
37 * 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
38 * way to make room for the Etherboot features that need substantial amounts
39 * of code like the ANSI console support. Currently the buffer is just below
40 * 0x10000, so this even conforms to the tagged boot image specification,
41 * which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
42 * interpretation of this "reserved" is that Etherboot may do whatever it
43 * likes, as long as its environment is kept intact (like the BIOS
44 * variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms
45 * were that if Etherboot was left at the boot menu for several minutes, the
46 * first eth_poll failed. Seems like I am the only person who does this.
47 * First of all I fixed the debugging code and then set out for a long bug
48 * hunting session. It took me about a week full time work - poking around
49 * various places in the driver, reading Don Becker's and Jeff Garzik's Linux
50 * driver and even the FreeBSD driver (what a piece of crap!) - and
51 * eventually spotted the nasty thing: the transmit routine was acknowledging
52 * each and every interrupt pending, including the RxOverrun and RxFIFIOver
53 * interrupts. This confused the RTL8139 thoroughly. It destroyed the
54 * Rx ring contents by dumping the 2K FIFO contents right where we wanted to
55 * get the next packet. Oh well, what fun.
56 *
57 * 18 Jan 2000 mdc@thinguin.org (Marty Connor)
58 * Drastically simplified error handling. Basically, if any error
59 * in transmission or reception occurs, the card is reset.
60 * Also, pointed all transmit descriptors to the same buffer to
61 * save buffer space. This should decrease driver size and avoid
62 * corruption because of exceeding 32K during runtime.
63 *
64 * 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
65 * rtl8139_recv was quite broken: it used the RxOK interrupt flag instead
66 * of the RxBufferEmpty flag which often resulted in very bad
67 * transmission performace - below 1kBytes/s.
68 *
69 */
70
71 #include <common.h>
72 #include <cpu_func.h>
73 #include <dm.h>
74 #include <log.h>
75 #include <malloc.h>
76 #include <net.h>
77 #include <netdev.h>
78 #include <asm/io.h>
79 #include <pci.h>
80 #include <linux/bitops.h>
81 #include <linux/delay.h>
82 #include <linux/types.h>
83
84 #define RTL_TIMEOUT 100000
85
86 /* PCI Tuning Parameters */
87 /* Threshold is bytes transferred to chip before transmission starts. */
88 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
89 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
90 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
91 #define TX_DMA_BURST 4 /* Calculate as 16<<val. */
92 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
93 #define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
94 #define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
95 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
96
97 #define DEBUG_TX 0 /* set to 1 to enable debug code */
98 #define DEBUG_RX 0 /* set to 1 to enable debug code */
99
100 #ifdef CONFIG_DM_ETH
101 #define bus_to_phys(devno, a) dm_pci_mem_to_phys((devno), (a))
102 #define phys_to_bus(devno, a) dm_pci_phys_to_mem((devno), (a))
103 #else
104 #define bus_to_phys(devno, a) pci_mem_to_phys((pci_dev_t)(devno), (a))
105 #define phys_to_bus(devno, a) pci_phys_to_mem((pci_dev_t)(devno), (a))
106 #endif
107
108 /* Symbolic offsets to registers. */
109 /* Ethernet hardware address. */
110 #define RTL_REG_MAC0 0x00
111 /* Multicast filter. */
112 #define RTL_REG_MAR0 0x08
113 /* Transmit status (four 32bit registers). */
114 #define RTL_REG_TXSTATUS0 0x10
115 /* Tx descriptors (also four 32bit). */
116 #define RTL_REG_TXADDR0 0x20
117 #define RTL_REG_RXBUF 0x30
118 #define RTL_REG_RXEARLYCNT 0x34
119 #define RTL_REG_RXEARLYSTATUS 0x36
120 #define RTL_REG_CHIPCMD 0x37
121 #define RTL_REG_CHIPCMD_CMDRESET BIT(4)
122 #define RTL_REG_CHIPCMD_CMDRXENB BIT(3)
123 #define RTL_REG_CHIPCMD_CMDTXENB BIT(2)
124 #define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0)
125 #define RTL_REG_RXBUFPTR 0x38
126 #define RTL_REG_RXBUFADDR 0x3A
127 #define RTL_REG_INTRMASK 0x3C
128 #define RTL_REG_INTRSTATUS 0x3E
129 #define RTL_REG_INTRSTATUS_PCIERR BIT(15)
130 #define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14)
131 #define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13)
132 #define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6)
133 #define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5)
134 #define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4)
135 #define RTL_REG_INTRSTATUS_TXERR BIT(3)
136 #define RTL_REG_INTRSTATUS_TXOK BIT(2)
137 #define RTL_REG_INTRSTATUS_RXERR BIT(1)
138 #define RTL_REG_INTRSTATUS_RXOK BIT(0)
139 #define RTL_REG_TXCONFIG 0x40
140 #define RTL_REG_RXCONFIG 0x44
141 #define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7)
142 #define RTL_REG_RXCONFIG_ACCEPTERR BIT(5)
143 #define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4)
144 #define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3)
145 #define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2)
146 #define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1)
147 #define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0)
148 /* general-purpose counter. */
149 #define RTL_REG_TIMER 0x48
150 /* 24 bits valid, write clears. */
151 #define RTL_REG_RXMISSED 0x4C
152 #define RTL_REG_CFG9346 0x50
153 #define RTL_REG_CONFIG0 0x51
154 #define RTL_REG_CONFIG1 0x52
155 /* intr if gp counter reaches this value */
156 #define RTL_REG_TIMERINTRREG 0x54
157 #define RTL_REG_MEDIASTATUS 0x58
158 #define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7)
159 #define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6)
160 #define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3)
161 #define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2)
162 #define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1)
163 #define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0)
164 #define RTL_REG_CONFIG3 0x59
165 #define RTL_REG_MULTIINTR 0x5C
166 /* revision of the RTL8139 chip */
167 #define RTL_REG_REVISIONID 0x5E
168 #define RTL_REG_TXSUMMARY 0x60
169 #define RTL_REG_MII_BMCR 0x62
170 #define RTL_REG_MII_BMSR 0x64
171 #define RTL_REG_NWAYADVERT 0x66
172 #define RTL_REG_NWAYLPAR 0x68
173 #define RTL_REG_NWAYEXPANSION 0x6A
174 #define RTL_REG_DISCONNECTCNT 0x6C
175 #define RTL_REG_FALSECARRIERCNT 0x6E
176 #define RTL_REG_NWAYTESTREG 0x70
177 /* packet received counter */
178 #define RTL_REG_RXCNT 0x72
179 /* chip status and configuration register */
180 #define RTL_REG_CSCR 0x74
181 #define RTL_REG_PHYPARM1 0x78
182 #define RTL_REG_TWISTERPARM 0x7c
183 /* undocumented */
184 #define RTL_REG_PHYPARM2 0x80
185 /*
186 * from 0x84 onwards are a number of power management/wakeup frame
187 * definitions we will probably never need to know about.
188 */
189
190 #define RTL_STS_RXMULTICAST BIT(15)
191 #define RTL_STS_RXPHYSICAL BIT(14)
192 #define RTL_STS_RXBROADCAST BIT(13)
193 #define RTL_STS_RXBADSYMBOL BIT(5)
194 #define RTL_STS_RXRUNT BIT(4)
195 #define RTL_STS_RXTOOLONG BIT(3)
196 #define RTL_STS_RXCRCERR BIT(2)
197 #define RTL_STS_RXBADALIGN BIT(1)
198 #define RTL_STS_RXSTATUSOK BIT(0)
199
200 struct rtl8139_priv {
201 #ifndef CONFIG_DM_ETH
202 struct eth_device dev;
203 pci_dev_t devno;
204 #else
205 struct udevice *devno;
206 #endif
207 unsigned int rxstatus;
208 unsigned int cur_rx;
209 unsigned int cur_tx;
210 unsigned long ioaddr;
211 unsigned char enetaddr[6];
212 };
213
214 /* The RTL8139 can only transmit from a contiguous, aligned memory block. */
215 static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4);
216 static unsigned char rx_ring[RX_BUF_LEN + 16] __aligned(4);
217
218 /* Serial EEPROM section. */
219
220 /* EEPROM_Ctrl bits. */
221 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
222 #define EE_CS 0x08 /* EEPROM chip select. */
223 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
224 #define EE_WRITE_0 0x00
225 #define EE_WRITE_1 0x02
226 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
227 #define EE_ENB (0x80 | EE_CS)
228
229 /* The EEPROM commands include the alway-set leading bit. */
230 #define EE_WRITE_CMD 5
231 #define EE_READ_CMD 6
232 #define EE_ERASE_CMD 7
233
rtl8139_eeprom_delay(struct rtl8139_priv * priv)234 static void rtl8139_eeprom_delay(struct rtl8139_priv *priv)
235 {
236 /*
237 * Delay between EEPROM clock transitions.
238 * No extra delay is needed with 33MHz PCI, but 66MHz may change this.
239 */
240 inl(priv->ioaddr + RTL_REG_CFG9346);
241 }
242
rtl8139_read_eeprom(struct rtl8139_priv * priv,unsigned int location,unsigned int addr_len)243 static int rtl8139_read_eeprom(struct rtl8139_priv *priv,
244 unsigned int location, unsigned int addr_len)
245 {
246 unsigned int read_cmd = location | (EE_READ_CMD << addr_len);
247 uintptr_t ee_addr = priv->ioaddr + RTL_REG_CFG9346;
248 unsigned int retval = 0;
249 u8 dataval;
250 int i;
251
252 outb(EE_ENB & ~EE_CS, ee_addr);
253 outb(EE_ENB, ee_addr);
254 rtl8139_eeprom_delay(priv);
255
256 /* Shift the read command bits out. */
257 for (i = 4 + addr_len; i >= 0; i--) {
258 dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0;
259 outb(EE_ENB | dataval, ee_addr);
260 rtl8139_eeprom_delay(priv);
261 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
262 rtl8139_eeprom_delay(priv);
263 }
264
265 outb(EE_ENB, ee_addr);
266 rtl8139_eeprom_delay(priv);
267
268 for (i = 16; i > 0; i--) {
269 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
270 rtl8139_eeprom_delay(priv);
271 retval <<= 1;
272 retval |= inb(ee_addr) & EE_DATA_READ;
273 outb(EE_ENB, ee_addr);
274 rtl8139_eeprom_delay(priv);
275 }
276
277 /* Terminate the EEPROM access. */
278 outb(~EE_CS, ee_addr);
279 rtl8139_eeprom_delay(priv);
280
281 return retval;
282 }
283
284 static const unsigned int rtl8139_rx_config =
285 (RX_BUF_LEN_IDX << 11) |
286 (RX_FIFO_THRESH << 13) |
287 (RX_DMA_BURST << 8);
288
rtl8139_set_rx_mode(struct rtl8139_priv * priv)289 static void rtl8139_set_rx_mode(struct rtl8139_priv *priv)
290 {
291 /* !IFF_PROMISC */
292 unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST |
293 RTL_REG_RXCONFIG_ACCEPTMULTICAST |
294 RTL_REG_RXCONFIG_ACCEPTMYPHYS;
295
296 outl(rtl8139_rx_config | rx_mode, priv->ioaddr + RTL_REG_RXCONFIG);
297
298 outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 0);
299 outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 4);
300 }
301
rtl8139_hw_reset(struct rtl8139_priv * priv)302 static void rtl8139_hw_reset(struct rtl8139_priv *priv)
303 {
304 u8 reg;
305 int i;
306
307 outb(RTL_REG_CHIPCMD_CMDRESET, priv->ioaddr + RTL_REG_CHIPCMD);
308
309 /* Give the chip 10ms to finish the reset. */
310 for (i = 0; i < 100; i++) {
311 reg = inb(priv->ioaddr + RTL_REG_CHIPCMD);
312 if (!(reg & RTL_REG_CHIPCMD_CMDRESET))
313 break;
314
315 udelay(100);
316 }
317 }
318
rtl8139_reset(struct rtl8139_priv * priv)319 static void rtl8139_reset(struct rtl8139_priv *priv)
320 {
321 int i;
322
323 priv->cur_rx = 0;
324 priv->cur_tx = 0;
325
326 rtl8139_hw_reset(priv);
327
328 for (i = 0; i < ETH_ALEN; i++)
329 outb(priv->enetaddr[i], priv->ioaddr + RTL_REG_MAC0 + i);
330
331 /* Must enable Tx/Rx before setting transfer thresholds! */
332 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
333 priv->ioaddr + RTL_REG_CHIPCMD);
334
335 /* accept no frames yet! */
336 outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG);
337 outl((TX_DMA_BURST << 8) | 0x03000000, priv->ioaddr + RTL_REG_TXCONFIG);
338
339 /*
340 * The Linux driver changes RTL_REG_CONFIG1 here to use a different
341 * LED pattern for half duplex or full/autodetect duplex (for
342 * full/autodetect, the outputs are TX/RX, Link10/100, FULL, while
343 * for half duplex it uses TX/RX, Link100, Link10). This is messy,
344 * because it doesn't match the inscription on the mounting bracket.
345 * It should not be changed from the configuration EEPROM default,
346 * because the card manufacturer should have set that to match the
347 * card.
348 */
349 debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring);
350
351 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
352 outl(phys_to_bus(priv->devno, (int)rx_ring), priv->ioaddr + RTL_REG_RXBUF);
353
354 /*
355 * If we add multicast support, the RTL_REG_MAR0 register would have
356 * to be initialized to 0xffffffffffffffff (two 32 bit accesses).
357 * Etherboot only needs broadcast (for ARP/RARP/BOOTP/DHCP) and
358 * unicast.
359 */
360 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
361 priv->ioaddr + RTL_REG_CHIPCMD);
362
363 outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG);
364
365 /* Start the chip's Tx and Rx process. */
366 outl(0, priv->ioaddr + RTL_REG_RXMISSED);
367
368 rtl8139_set_rx_mode(priv);
369
370 /* Disable all known interrupts by setting the interrupt mask. */
371 outw(0, priv->ioaddr + RTL_REG_INTRMASK);
372 }
373
rtl8139_send_common(struct rtl8139_priv * priv,void * packet,int length)374 static int rtl8139_send_common(struct rtl8139_priv *priv,
375 void *packet, int length)
376 {
377 unsigned int len = length;
378 unsigned long txstatus;
379 unsigned int status;
380 int i = 0;
381
382 memcpy(tx_buffer, packet, length);
383
384 debug_cond(DEBUG_TX, "sending %d bytes\n", len);
385
386 /*
387 * Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
388 * bytes are sent automatically for the FCS, totalling to 64 bytes).
389 */
390 while (len < ETH_ZLEN)
391 tx_buffer[len++] = '\0';
392
393 flush_cache((unsigned long)tx_buffer, length);
394 outl(phys_to_bus(priv->devno, (unsigned long)tx_buffer),
395 priv->ioaddr + RTL_REG_TXADDR0 + priv->cur_tx * 4);
396 outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len,
397 priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4);
398
399 do {
400 status = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
401 /*
402 * Only acknlowledge interrupt sources we can properly
403 * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/
404 * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the
405 * rtl8139_recv() function.
406 */
407 status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR |
408 RTL_REG_INTRSTATUS_PCIERR;
409 outw(status, priv->ioaddr + RTL_REG_INTRSTATUS);
410 if (status)
411 break;
412
413 udelay(10);
414 } while (i++ < RTL_TIMEOUT);
415
416 txstatus = inl(priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4);
417
418 if (!(status & RTL_REG_INTRSTATUS_TXOK)) {
419 debug_cond(DEBUG_TX,
420 "tx timeout/error (%d usecs), status %hX txstatus %lX\n",
421 10 * i, status, txstatus);
422
423 rtl8139_reset(priv);
424
425 return 0;
426 }
427
428 priv->cur_tx = (priv->cur_tx + 1) % NUM_TX_DESC;
429
430 debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n",
431 status, txstatus);
432
433 return length;
434 }
435
rtl8139_recv_common(struct rtl8139_priv * priv,unsigned char * rxdata,uchar ** packetp)436 static int rtl8139_recv_common(struct rtl8139_priv *priv, unsigned char *rxdata,
437 uchar **packetp)
438 {
439 const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
440 RTL_REG_INTRSTATUS_RXOVERFLOW |
441 RTL_REG_INTRSTATUS_RXOK;
442 unsigned int rx_size, rx_status;
443 unsigned int ring_offs;
444 int length = 0;
445
446 if (inb(priv->ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
447 return 0;
448
449 priv->rxstatus = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
450 /* See below for the rest of the interrupt acknowledges. */
451 outw(priv->rxstatus & ~rxstat, priv->ioaddr + RTL_REG_INTRSTATUS);
452
453 debug_cond(DEBUG_RX, "%s: int %hX ", __func__, priv->rxstatus);
454
455 ring_offs = priv->cur_rx % RX_BUF_LEN;
456 /* ring_offs is guaranteed being 4-byte aligned */
457 rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
458 rx_size = rx_status >> 16;
459 rx_status &= 0xffff;
460
461 if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT |
462 RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR |
463 RTL_STS_RXBADALIGN)) ||
464 (rx_size < ETH_ZLEN) ||
465 (rx_size > ETH_FRAME_LEN + 4)) {
466 printf("rx error %hX\n", rx_status);
467 /* this clears all interrupts still pending */
468 rtl8139_reset(priv);
469 return 0;
470 }
471
472 /* Received a good packet */
473 length = rx_size - 4; /* no one cares about the FCS */
474 if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) {
475 int semi_count = RX_BUF_LEN - ring_offs - 4;
476
477 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
478 memcpy(&rxdata[semi_count], rx_ring,
479 rx_size - 4 - semi_count);
480
481 *packetp = rxdata;
482 debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
483 semi_count, rx_size - 4 - semi_count);
484 } else {
485 *packetp = rx_ring + ring_offs + 4;
486 debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4);
487 }
488
489 return length;
490 }
491
rtl8139_free_pkt_common(struct rtl8139_priv * priv,unsigned int len)492 static int rtl8139_free_pkt_common(struct rtl8139_priv *priv, unsigned int len)
493 {
494 const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
495 RTL_REG_INTRSTATUS_RXOVERFLOW |
496 RTL_REG_INTRSTATUS_RXOK;
497 unsigned int rx_size = len + 4;
498
499 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
500
501 priv->cur_rx = ROUND(priv->cur_rx + rx_size + 4, 4);
502 outw(priv->cur_rx - 16, priv->ioaddr + RTL_REG_RXBUFPTR);
503 /*
504 * See RTL8139 Programming Guide V0.1 for the official handling of
505 * Rx overflow situations. The document itself contains basically
506 * no usable information, except for a few exception handling rules.
507 */
508 outw(priv->rxstatus & rxstat, priv->ioaddr + RTL_REG_INTRSTATUS);
509
510 return 0;
511 }
512
rtl8139_init_common(struct rtl8139_priv * priv)513 static int rtl8139_init_common(struct rtl8139_priv *priv)
514 {
515 u8 reg;
516
517 /* Bring the chip out of low-power mode. */
518 outb(0x00, priv->ioaddr + RTL_REG_CONFIG1);
519
520 rtl8139_reset(priv);
521
522 reg = inb(priv->ioaddr + RTL_REG_MEDIASTATUS);
523 if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) {
524 printf("Cable not connected or other link failure\n");
525 return -1;
526 }
527
528 return 0;
529 }
530
rtl8139_stop_common(struct rtl8139_priv * priv)531 static void rtl8139_stop_common(struct rtl8139_priv *priv)
532 {
533 rtl8139_hw_reset(priv);
534 }
535
rtl8139_get_hwaddr(struct rtl8139_priv * priv)536 static void rtl8139_get_hwaddr(struct rtl8139_priv *priv)
537 {
538 unsigned short *ap = (unsigned short *)priv->enetaddr;
539 int i, addr_len;
540
541 /* Bring the chip out of low-power mode. */
542 outb(0x00, priv->ioaddr + RTL_REG_CONFIG1);
543
544 addr_len = rtl8139_read_eeprom(priv, 0, 8) == 0x8129 ? 8 : 6;
545 for (i = 0; i < 3; i++)
546 *ap++ = le16_to_cpu(rtl8139_read_eeprom(priv, i + 7, addr_len));
547 }
548
rtl8139_name(char * str,int card_number)549 static void rtl8139_name(char *str, int card_number)
550 {
551 sprintf(str, "RTL8139#%u", card_number);
552 }
553
554 static struct pci_device_id supported[] = {
555 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139) },
556 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139) },
557 { }
558 };
559
560 #ifndef CONFIG_DM_ETH
rtl8139_bcast_addr(struct eth_device * dev,const u8 * bcast_mac,int join)561 static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac,
562 int join)
563 {
564 return 0;
565 }
566
rtl8139_init(struct eth_device * dev,struct bd_info * bis)567 static int rtl8139_init(struct eth_device *dev, struct bd_info *bis)
568 {
569 struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
570
571 return rtl8139_init_common(priv);
572 }
573
rtl8139_stop(struct eth_device * dev)574 static void rtl8139_stop(struct eth_device *dev)
575 {
576 struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
577
578 return rtl8139_stop_common(priv);
579 }
580
rtl8139_send(struct eth_device * dev,void * packet,int length)581 static int rtl8139_send(struct eth_device *dev, void *packet, int length)
582 {
583 struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
584
585 return rtl8139_send_common(priv, packet, length);
586 }
587
rtl8139_recv(struct eth_device * dev)588 static int rtl8139_recv(struct eth_device *dev)
589 {
590 struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
591 unsigned char rxdata[RX_BUF_LEN];
592 uchar *packet;
593 int ret;
594
595 ret = rtl8139_recv_common(priv, rxdata, &packet);
596 if (ret) {
597 net_process_received_packet(packet, ret);
598 rtl8139_free_pkt_common(priv, ret);
599 }
600
601 return ret;
602 }
603
rtl8139_initialize(struct bd_info * bis)604 int rtl8139_initialize(struct bd_info *bis)
605 {
606 struct rtl8139_priv *priv;
607 struct eth_device *dev;
608 int card_number = 0;
609 pci_dev_t devno;
610 int idx = 0;
611 u32 iobase;
612
613 while (1) {
614 /* Find RTL8139 */
615 devno = pci_find_devices(supported, idx++);
616 if (devno < 0)
617 break;
618
619 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
620 iobase &= ~0xf;
621
622 debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
623
624 priv = calloc(1, sizeof(*priv));
625 if (!priv) {
626 printf("Can not allocate memory of rtl8139\n");
627 break;
628 }
629
630 priv->devno = devno;
631 priv->ioaddr = (unsigned long)bus_to_phys(devno, iobase);
632
633 dev = &priv->dev;
634
635 rtl8139_name(dev->name, card_number);
636
637 dev->iobase = priv->ioaddr; /* Non-DM compatibility */
638 dev->init = rtl8139_init;
639 dev->halt = rtl8139_stop;
640 dev->send = rtl8139_send;
641 dev->recv = rtl8139_recv;
642 dev->mcast = rtl8139_bcast_addr;
643
644 rtl8139_get_hwaddr(priv);
645
646 /* Non-DM compatibility */
647 memcpy(priv->dev.enetaddr, priv->enetaddr, 6);
648
649 eth_register(dev);
650
651 card_number++;
652
653 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
654
655 udelay(10 * 1000);
656 }
657
658 return card_number;
659 }
660 #else /* DM_ETH */
rtl8139_start(struct udevice * dev)661 static int rtl8139_start(struct udevice *dev)
662 {
663 struct eth_pdata *plat = dev_get_plat(dev);
664 struct rtl8139_priv *priv = dev_get_priv(dev);
665
666 memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
667
668 return rtl8139_init_common(priv);
669 }
670
rtl8139_stop(struct udevice * dev)671 static void rtl8139_stop(struct udevice *dev)
672 {
673 struct rtl8139_priv *priv = dev_get_priv(dev);
674
675 rtl8139_stop_common(priv);
676 }
677
rtl8139_send(struct udevice * dev,void * packet,int length)678 static int rtl8139_send(struct udevice *dev, void *packet, int length)
679 {
680 struct rtl8139_priv *priv = dev_get_priv(dev);
681 int ret;
682
683 ret = rtl8139_send_common(priv, packet, length);
684
685 return ret ? 0 : -ETIMEDOUT;
686 }
687
rtl8139_recv(struct udevice * dev,int flags,uchar ** packetp)688 static int rtl8139_recv(struct udevice *dev, int flags, uchar **packetp)
689 {
690 struct rtl8139_priv *priv = dev_get_priv(dev);
691 static unsigned char rxdata[RX_BUF_LEN];
692
693 return rtl8139_recv_common(priv, rxdata, packetp);
694 }
695
rtl8139_free_pkt(struct udevice * dev,uchar * packet,int length)696 static int rtl8139_free_pkt(struct udevice *dev, uchar *packet, int length)
697 {
698 struct rtl8139_priv *priv = dev_get_priv(dev);
699
700 rtl8139_free_pkt_common(priv, length);
701
702 return 0;
703 }
704
rtl8139_write_hwaddr(struct udevice * dev)705 static int rtl8139_write_hwaddr(struct udevice *dev)
706 {
707 struct eth_pdata *plat = dev_get_plat(dev);
708 struct rtl8139_priv *priv = dev_get_priv(dev);
709
710 memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
711
712 rtl8139_reset(priv);
713
714 return 0;
715 }
716
rtl8139_read_rom_hwaddr(struct udevice * dev)717 static int rtl8139_read_rom_hwaddr(struct udevice *dev)
718 {
719 struct rtl8139_priv *priv = dev_get_priv(dev);
720
721 rtl8139_get_hwaddr(priv);
722
723 return 0;
724 }
725
rtl8139_bind(struct udevice * dev)726 static int rtl8139_bind(struct udevice *dev)
727 {
728 static int card_number;
729 char name[16];
730
731 rtl8139_name(name, card_number++);
732
733 return device_set_name(dev, name);
734 }
735
rtl8139_probe(struct udevice * dev)736 static int rtl8139_probe(struct udevice *dev)
737 {
738 struct eth_pdata *plat = dev_get_plat(dev);
739 struct rtl8139_priv *priv = dev_get_priv(dev);
740 u32 iobase;
741
742 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
743 iobase &= ~0xf;
744
745 debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
746
747 priv->devno = dev;
748 priv->ioaddr = (unsigned long)bus_to_phys(dev, iobase);
749
750 rtl8139_get_hwaddr(priv);
751 memcpy(plat->enetaddr, priv->enetaddr, sizeof(priv->enetaddr));
752
753 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
754
755 return 0;
756 }
757
758 static const struct eth_ops rtl8139_ops = {
759 .start = rtl8139_start,
760 .send = rtl8139_send,
761 .recv = rtl8139_recv,
762 .stop = rtl8139_stop,
763 .free_pkt = rtl8139_free_pkt,
764 .write_hwaddr = rtl8139_write_hwaddr,
765 .read_rom_hwaddr = rtl8139_read_rom_hwaddr,
766 };
767
768 U_BOOT_DRIVER(eth_rtl8139) = {
769 .name = "eth_rtl8139",
770 .id = UCLASS_ETH,
771 .bind = rtl8139_bind,
772 .probe = rtl8139_probe,
773 .ops = &rtl8139_ops,
774 .priv_auto = sizeof(struct rtl8139_priv),
775 .plat_auto = sizeof(struct eth_pdata),
776 };
777
778 U_BOOT_PCI_DEVICE(eth_rtl8139, supported);
779 #endif
780