1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007-2009 Michal Simek
4 * (C) Copyright 2003 Xilinx Inc.
5 *
6 * Michal SIMEK <monstr@monstr.eu>
7 */
8
9 #include <common.h>
10 #include <log.h>
11 #include <net.h>
12 #include <config.h>
13 #include <dm.h>
14 #include <console.h>
15 #include <malloc.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <phy.h>
19 #include <miiphy.h>
20 #include <fdtdec.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
23 #include <linux/kernel.h>
24 #include <asm/io.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #define ENET_ADDR_LENGTH 6
29 #define ETH_FCS_LEN 4 /* Octets in the FCS */
30
31 /* Xmit complete */
32 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
33 /* Xmit interrupt enable bit */
34 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL
35 /* Program the MAC address */
36 #define XEL_TSR_PROGRAM_MASK 0x00000002UL
37 /* define for programming the MAC address into the EMAC Lite */
38 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
39
40 /* Transmit packet length upper byte */
41 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
42 /* Transmit packet length lower byte */
43 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
44
45 /* Recv complete */
46 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL
47 /* Recv interrupt enable bit */
48 #define XEL_RSR_RECV_IE_MASK 0x00000008UL
49
50 /* MDIO Address Register Bit Masks */
51 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
52 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
53 #define XEL_MDIOADDR_PHYADR_SHIFT 5
54 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
55
56 /* MDIO Write Data Register Bit Masks */
57 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
58
59 /* MDIO Read Data Register Bit Masks */
60 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
61
62 /* MDIO Control Register Bit Masks */
63 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
64 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
65
66 struct emaclite_regs {
67 u32 tx_ping; /* 0x0 - TX Ping buffer */
68 u32 reserved1[504];
69 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
70 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
71 u32 mdiord;/* 0x7ec - MDIO Read Data Register */
72 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
73 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
74 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
75 u32 tx_ping_tsr; /* 0x7fc - Tx status */
76 u32 tx_pong; /* 0x800 - TX Pong buffer */
77 u32 reserved2[508];
78 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
79 u32 reserved3; /* 0xff8 */
80 u32 tx_pong_tsr; /* 0xffc - Tx status */
81 u32 rx_ping; /* 0x1000 - Receive Buffer */
82 u32 reserved4[510];
83 u32 rx_ping_rsr; /* 0x17fc - Rx status */
84 u32 rx_pong; /* 0x1800 - Receive Buffer */
85 u32 reserved5[510];
86 u32 rx_pong_rsr; /* 0x1ffc - Rx status */
87 };
88
89 struct xemaclite {
90 bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
91 u32 txpp; /* TX ping pong buffer */
92 u32 rxpp; /* RX ping pong buffer */
93 int phyaddr;
94 struct emaclite_regs *regs;
95 struct phy_device *phydev;
96 struct mii_dev *bus;
97 };
98
99 static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
100
xemaclite_alignedread(u32 * srcptr,void * destptr,u32 bytecount)101 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
102 {
103 u32 i;
104 u32 alignbuffer;
105 u32 *to32ptr;
106 u32 *from32ptr;
107 u8 *to8ptr;
108 u8 *from8ptr;
109
110 from32ptr = (u32 *) srcptr;
111
112 /* Word aligned buffer, no correction needed. */
113 to32ptr = (u32 *) destptr;
114 while (bytecount > 3) {
115 *to32ptr++ = *from32ptr++;
116 bytecount -= 4;
117 }
118 to8ptr = (u8 *) to32ptr;
119
120 alignbuffer = *from32ptr++;
121 from8ptr = (u8 *) &alignbuffer;
122
123 for (i = 0; i < bytecount; i++)
124 *to8ptr++ = *from8ptr++;
125 }
126
xemaclite_alignedwrite(void * srcptr,u32 * destptr,u32 bytecount)127 static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
128 {
129 u32 i;
130 u32 alignbuffer;
131 u32 *to32ptr = (u32 *) destptr;
132 u32 *from32ptr;
133 u8 *to8ptr;
134 u8 *from8ptr;
135
136 from32ptr = (u32 *) srcptr;
137 while (bytecount > 3) {
138
139 *to32ptr++ = *from32ptr++;
140 bytecount -= 4;
141 }
142
143 alignbuffer = 0;
144 to8ptr = (u8 *) &alignbuffer;
145 from8ptr = (u8 *) from32ptr;
146
147 for (i = 0; i < bytecount; i++)
148 *to8ptr++ = *from8ptr++;
149
150 *to32ptr++ = alignbuffer;
151 }
152
wait_for_bit(const char * func,u32 * reg,const u32 mask,bool set,unsigned int timeout)153 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
154 bool set, unsigned int timeout)
155 {
156 u32 val;
157 unsigned long start = get_timer(0);
158
159 while (1) {
160 val = __raw_readl(reg);
161
162 if (!set)
163 val = ~val;
164
165 if ((val & mask) == mask)
166 return 0;
167
168 if (get_timer(start) > timeout)
169 break;
170
171 if (ctrlc()) {
172 puts("Abort\n");
173 return -EINTR;
174 }
175
176 udelay(1);
177 }
178
179 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
180 func, reg, mask, set);
181
182 return -ETIMEDOUT;
183 }
184
mdio_wait(struct emaclite_regs * regs)185 static int mdio_wait(struct emaclite_regs *regs)
186 {
187 return wait_for_bit(__func__, ®s->mdioctrl,
188 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
189 }
190
phyread(struct xemaclite * emaclite,u32 phyaddress,u32 registernum,u16 * data)191 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
192 u16 *data)
193 {
194 struct emaclite_regs *regs = emaclite->regs;
195
196 if (mdio_wait(regs))
197 return 1;
198
199 u32 ctrl_reg = __raw_readl(®s->mdioctrl);
200 __raw_writel(XEL_MDIOADDR_OP_MASK
201 | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
202 | registernum), ®s->mdioaddr);
203 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
204
205 if (mdio_wait(regs))
206 return 1;
207
208 /* Read data */
209 *data = __raw_readl(®s->mdiord);
210 return 0;
211 }
212
phywrite(struct xemaclite * emaclite,u32 phyaddress,u32 registernum,u16 data)213 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
214 u16 data)
215 {
216 struct emaclite_regs *regs = emaclite->regs;
217
218 if (mdio_wait(regs))
219 return 1;
220
221 /*
222 * Write the PHY address, register number and clear the OP bit in the
223 * MDIO Address register and then write the value into the MDIO Write
224 * Data register. Finally, set the Status bit in the MDIO Control
225 * register to start a MDIO write transaction.
226 */
227 u32 ctrl_reg = __raw_readl(®s->mdioctrl);
228 __raw_writel(~XEL_MDIOADDR_OP_MASK
229 & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
230 | registernum), ®s->mdioaddr);
231 __raw_writel(data, ®s->mdiowr);
232 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
233
234 if (mdio_wait(regs))
235 return 1;
236
237 return 0;
238 }
239
emaclite_stop(struct udevice * dev)240 static void emaclite_stop(struct udevice *dev)
241 {
242 debug("eth_stop\n");
243 }
244
245 /* Use MII register 1 (MII status register) to detect PHY */
246 #define PHY_DETECT_REG 1
247
248 /* Mask used to verify certain PHY features (or register contents)
249 * in the register above:
250 * 0x1000: 10Mbps full duplex support
251 * 0x0800: 10Mbps half duplex support
252 * 0x0008: Auto-negotiation support
253 */
254 #define PHY_DETECT_MASK 0x1808
255
setup_phy(struct udevice * dev)256 static int setup_phy(struct udevice *dev)
257 {
258 int i, ret;
259 u16 phyreg;
260 struct xemaclite *emaclite = dev_get_priv(dev);
261 struct phy_device *phydev;
262
263 u32 supported = SUPPORTED_10baseT_Half |
264 SUPPORTED_10baseT_Full |
265 SUPPORTED_100baseT_Half |
266 SUPPORTED_100baseT_Full;
267
268 if (emaclite->phyaddr != -1) {
269 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
270 if ((phyreg != 0xFFFF) &&
271 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
272 /* Found a valid PHY address */
273 debug("Default phy address %d is valid\n",
274 emaclite->phyaddr);
275 } else {
276 debug("PHY address is not setup correctly %d\n",
277 emaclite->phyaddr);
278 emaclite->phyaddr = -1;
279 }
280 }
281
282 if (emaclite->phyaddr == -1) {
283 /* detect the PHY address */
284 for (i = 31; i >= 0; i--) {
285 phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
286 if ((phyreg != 0xFFFF) &&
287 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
288 /* Found a valid PHY address */
289 emaclite->phyaddr = i;
290 debug("emaclite: Found valid phy address, %d\n",
291 i);
292 break;
293 }
294 }
295 }
296
297 /* interface - look at tsec */
298 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
299 PHY_INTERFACE_MODE_MII);
300 /*
301 * Phy can support 1000baseT but device NOT that's why phydev->supported
302 * must be setup for 1000baseT. phydev->advertising setups what speeds
303 * will be used for autonegotiation where 1000baseT must be disabled.
304 */
305 phydev->supported = supported | SUPPORTED_1000baseT_Half |
306 SUPPORTED_1000baseT_Full;
307 phydev->advertising = supported;
308 emaclite->phydev = phydev;
309 phy_config(phydev);
310 ret = phy_startup(phydev);
311 if (ret)
312 return ret;
313
314 if (!phydev->link) {
315 printf("%s: No link.\n", phydev->dev->name);
316 return 0;
317 }
318
319 /* Do not setup anything */
320 return 1;
321 }
322
emaclite_start(struct udevice * dev)323 static int emaclite_start(struct udevice *dev)
324 {
325 struct xemaclite *emaclite = dev_get_priv(dev);
326 struct eth_pdata *pdata = dev_get_plat(dev);
327 struct emaclite_regs *regs = emaclite->regs;
328
329 debug("EmacLite Initialization Started\n");
330
331 /*
332 * TX - TX_PING & TX_PONG initialization
333 */
334 /* Restart PING TX */
335 __raw_writel(0, ®s->tx_ping_tsr);
336 /* Copy MAC address */
337 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping,
338 ENET_ADDR_LENGTH);
339 /* Set the length */
340 __raw_writel(ENET_ADDR_LENGTH, ®s->tx_ping_tplr);
341 /* Update the MAC address in the EMAC Lite */
342 __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_ping_tsr);
343 /* Wait for EMAC Lite to finish with the MAC address update */
344 while ((__raw_readl(®s->tx_ping_tsr) &
345 XEL_TSR_PROG_MAC_ADDR) != 0)
346 ;
347
348 if (emaclite->txpp) {
349 /* The same operation with PONG TX */
350 __raw_writel(0, ®s->tx_pong_tsr);
351 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong,
352 ENET_ADDR_LENGTH);
353 __raw_writel(ENET_ADDR_LENGTH, ®s->tx_pong_tplr);
354 __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_pong_tsr);
355 while ((__raw_readl(®s->tx_pong_tsr) &
356 XEL_TSR_PROG_MAC_ADDR) != 0)
357 ;
358 }
359
360 /*
361 * RX - RX_PING & RX_PONG initialization
362 */
363 /* Write out the value to flush the RX buffer */
364 __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_ping_rsr);
365
366 if (emaclite->rxpp)
367 __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_pong_rsr);
368
369 __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, ®s->mdioctrl);
370 if (__raw_readl(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
371 if (!setup_phy(dev))
372 return -1;
373
374 debug("EmacLite Initialization complete\n");
375 return 0;
376 }
377
xemaclite_txbufferavailable(struct xemaclite * emaclite)378 static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
379 {
380 u32 tmp;
381 struct emaclite_regs *regs = emaclite->regs;
382
383 /*
384 * Read the other buffer register
385 * and determine if the other buffer is available
386 */
387 tmp = ~__raw_readl(®s->tx_ping_tsr);
388 if (emaclite->txpp)
389 tmp |= ~__raw_readl(®s->tx_pong_tsr);
390
391 return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
392 }
393
emaclite_send(struct udevice * dev,void * ptr,int len)394 static int emaclite_send(struct udevice *dev, void *ptr, int len)
395 {
396 u32 reg;
397 struct xemaclite *emaclite = dev_get_priv(dev);
398 struct emaclite_regs *regs = emaclite->regs;
399
400 u32 maxtry = 1000;
401
402 if (len > PKTSIZE)
403 len = PKTSIZE;
404
405 while (xemaclite_txbufferavailable(emaclite) && maxtry) {
406 udelay(10);
407 maxtry--;
408 }
409
410 if (!maxtry) {
411 printf("Error: Timeout waiting for ethernet TX buffer\n");
412 /* Restart PING TX */
413 __raw_writel(0, ®s->tx_ping_tsr);
414 if (emaclite->txpp) {
415 __raw_writel(0, ®s->tx_pong_tsr);
416 }
417 return -1;
418 }
419
420 /* Determine if the expected buffer address is empty */
421 reg = __raw_readl(®s->tx_ping_tsr);
422 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
423 debug("Send packet from tx_ping buffer\n");
424 /* Write the frame to the buffer */
425 xemaclite_alignedwrite(ptr, ®s->tx_ping, len);
426 __raw_writel(len
427 & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
428 ®s->tx_ping_tplr);
429 reg = __raw_readl(®s->tx_ping_tsr);
430 reg |= XEL_TSR_XMIT_BUSY_MASK;
431 __raw_writel(reg, ®s->tx_ping_tsr);
432 return 0;
433 }
434
435 if (emaclite->txpp) {
436 /* Determine if the expected buffer address is empty */
437 reg = __raw_readl(®s->tx_pong_tsr);
438 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
439 debug("Send packet from tx_pong buffer\n");
440 /* Write the frame to the buffer */
441 xemaclite_alignedwrite(ptr, ®s->tx_pong, len);
442 __raw_writel(len &
443 (XEL_TPLR_LENGTH_MASK_HI |
444 XEL_TPLR_LENGTH_MASK_LO),
445 ®s->tx_pong_tplr);
446 reg = __raw_readl(®s->tx_pong_tsr);
447 reg |= XEL_TSR_XMIT_BUSY_MASK;
448 __raw_writel(reg, ®s->tx_pong_tsr);
449 return 0;
450 }
451 }
452
453 puts("Error while sending frame\n");
454 return -1;
455 }
456
emaclite_recv(struct udevice * dev,int flags,uchar ** packetp)457 static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
458 {
459 u32 length, first_read, reg, attempt = 0;
460 void *addr, *ack;
461 struct xemaclite *emaclite = dev_get_priv(dev);
462 struct emaclite_regs *regs = emaclite->regs;
463 struct ethernet_hdr *eth;
464 struct ip_udp_hdr *ip;
465
466 try_again:
467 if (!emaclite->use_rx_pong_buffer_next) {
468 reg = __raw_readl(®s->rx_ping_rsr);
469 debug("Testing data at rx_ping\n");
470 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
471 debug("Data found in rx_ping buffer\n");
472 addr = ®s->rx_ping;
473 ack = ®s->rx_ping_rsr;
474 } else {
475 debug("Data not found in rx_ping buffer\n");
476 /* Pong buffer is not available - return immediately */
477 if (!emaclite->rxpp)
478 return -1;
479
480 /* Try pong buffer if this is first attempt */
481 if (attempt++)
482 return -1;
483 emaclite->use_rx_pong_buffer_next =
484 !emaclite->use_rx_pong_buffer_next;
485 goto try_again;
486 }
487 } else {
488 reg = __raw_readl(®s->rx_pong_rsr);
489 debug("Testing data at rx_pong\n");
490 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
491 debug("Data found in rx_pong buffer\n");
492 addr = ®s->rx_pong;
493 ack = ®s->rx_pong_rsr;
494 } else {
495 debug("Data not found in rx_pong buffer\n");
496 /* Try ping buffer if this is first attempt */
497 if (attempt++)
498 return -1;
499 emaclite->use_rx_pong_buffer_next =
500 !emaclite->use_rx_pong_buffer_next;
501 goto try_again;
502 }
503 }
504
505 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
506 first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
507 xemaclite_alignedread(addr, etherrxbuff, first_read);
508
509 /* Detect real packet size */
510 eth = (struct ethernet_hdr *)etherrxbuff;
511 switch (ntohs(eth->et_protlen)) {
512 case PROT_ARP:
513 length = first_read;
514 debug("ARP Packet %x\n", length);
515 break;
516 case PROT_IP:
517 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
518 length = ntohs(ip->ip_len);
519 length += ETHER_HDR_SIZE + ETH_FCS_LEN;
520 debug("IP Packet %x\n", length);
521 break;
522 default:
523 debug("Other Packet\n");
524 length = PKTSIZE;
525 break;
526 }
527
528 /* Read the rest of the packet which is longer then first read */
529 if (length != first_read)
530 xemaclite_alignedread(addr + first_read,
531 etherrxbuff + first_read,
532 length - first_read);
533
534 /* Acknowledge the frame */
535 reg = __raw_readl(ack);
536 reg &= ~XEL_RSR_RECV_DONE_MASK;
537 __raw_writel(reg, ack);
538
539 debug("Packet receive from 0x%p, length %dB\n", addr, length);
540 *packetp = etherrxbuff;
541 return length;
542 }
543
emaclite_miiphy_read(struct mii_dev * bus,int addr,int devad,int reg)544 static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
545 int devad, int reg)
546 {
547 u32 ret;
548 u16 val = 0;
549
550 ret = phyread(bus->priv, addr, reg, &val);
551 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
552 return val;
553 }
554
emaclite_miiphy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)555 static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
556 int reg, u16 value)
557 {
558 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
559 return phywrite(bus->priv, addr, reg, value);
560 }
561
emaclite_probe(struct udevice * dev)562 static int emaclite_probe(struct udevice *dev)
563 {
564 struct xemaclite *emaclite = dev_get_priv(dev);
565 int ret;
566
567 emaclite->bus = mdio_alloc();
568 emaclite->bus->read = emaclite_miiphy_read;
569 emaclite->bus->write = emaclite_miiphy_write;
570 emaclite->bus->priv = emaclite;
571
572 ret = mdio_register_seq(emaclite->bus, dev_seq(dev));
573 if (ret)
574 return ret;
575
576 return 0;
577 }
578
emaclite_remove(struct udevice * dev)579 static int emaclite_remove(struct udevice *dev)
580 {
581 struct xemaclite *emaclite = dev_get_priv(dev);
582
583 free(emaclite->phydev);
584 mdio_unregister(emaclite->bus);
585 mdio_free(emaclite->bus);
586
587 return 0;
588 }
589
590 static const struct eth_ops emaclite_ops = {
591 .start = emaclite_start,
592 .send = emaclite_send,
593 .recv = emaclite_recv,
594 .stop = emaclite_stop,
595 };
596
emaclite_of_to_plat(struct udevice * dev)597 static int emaclite_of_to_plat(struct udevice *dev)
598 {
599 struct eth_pdata *pdata = dev_get_plat(dev);
600 struct xemaclite *emaclite = dev_get_priv(dev);
601 int offset = 0;
602
603 pdata->iobase = dev_read_addr(dev);
604 emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
605 0x10000);
606
607 emaclite->phyaddr = -1;
608
609 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
610 "phy-handle");
611 if (offset > 0)
612 emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
613 "reg", -1);
614
615 emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
616 "xlnx,tx-ping-pong", 0);
617 emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
618 "xlnx,rx-ping-pong", 0);
619
620 printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
621 emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
622
623 return 0;
624 }
625
626 static const struct udevice_id emaclite_ids[] = {
627 { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
628 { }
629 };
630
631 U_BOOT_DRIVER(emaclite) = {
632 .name = "emaclite",
633 .id = UCLASS_ETH,
634 .of_match = emaclite_ids,
635 .of_to_plat = emaclite_of_to_plat,
636 .probe = emaclite_probe,
637 .remove = emaclite_remove,
638 .ops = &emaclite_ops,
639 .priv_auto = sizeof(struct xemaclite),
640 .plat_auto = sizeof(struct eth_pdata),
641 };
642