1 /*
2 * ***************************************************************************
3 * Copyright (C) 2015 Marvell International Ltd.
4 * ***************************************************************************
5 * This program is free software: you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the Free
7 * Software Foundation, either version 2 of the License, or any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * ***************************************************************************
17 */
18 /* pcie_advk.c
19 *
20 * Ported from Linux driver - driver/pci/host/pci-aardvark.c
21 *
22 * Author: Victor Gu <xigu@marvell.com>
23 * Hezi Shahmoon <hezi.shahmoon@marvell.com>
24 *
25 */
26
27 #include <common.h>
28 #include <dm.h>
29 #include <pci.h>
30 #include <asm/io.h>
31 #include <asm-generic/gpio.h>
32 #include <dm/device_compat.h>
33 #include <linux/bitops.h>
34 #include <linux/delay.h>
35 #include <linux/ioport.h>
36
37 /* PCIe core registers */
38 #define PCIE_CORE_CMD_STATUS_REG 0x4
39 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
40 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
41 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
42 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
43 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
44 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
45 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE 0x2
46 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT 5
47 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE 0x2
48 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
49 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
50 #define PCIE_CORE_LINK_TRAINING BIT(5)
51 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
52 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
53 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
54 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7)
55 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8)
56
57 /* PIO registers base address and register offsets */
58 #define PIO_BASE_ADDR 0x4000
59 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
60 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
61 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
62 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
63 #define PIO_COMPLETION_STATUS_SHIFT 7
64 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
65 #define PIO_COMPLETION_STATUS_OK 0
66 #define PIO_COMPLETION_STATUS_UR 1
67 #define PIO_COMPLETION_STATUS_CRS 2
68 #define PIO_COMPLETION_STATUS_CA 4
69 #define PIO_NON_POSTED_REQ BIT(10)
70 #define PIO_ERR_STATUS BIT(11)
71 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
72 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
73 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
74 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
75 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
76 #define PIO_START (PIO_BASE_ADDR + 0x1c)
77 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
78
79 /* Aardvark Control registers */
80 #define CONTROL_BASE_ADDR 0x4800
81 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
82 #define PCIE_GEN_SEL_MSK 0x3
83 #define PCIE_GEN_SEL_SHIFT 0x0
84 #define SPEED_GEN_1 0
85 #define SPEED_GEN_2 1
86 #define SPEED_GEN_3 2
87 #define IS_RC_MSK 1
88 #define IS_RC_SHIFT 2
89 #define LANE_CNT_MSK 0x18
90 #define LANE_CNT_SHIFT 0x3
91 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
92 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
93 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
94 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
95 #define LINK_TRAINING_EN BIT(6)
96 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
97 #define PCIE_CORE_CTRL2_RESERVED 0x7
98 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
99 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
100 #define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
101
102 /* LMI registers base address and register offsets */
103 #define LMI_BASE_ADDR 0x6000
104 #define CFG_REG (LMI_BASE_ADDR + 0x0)
105 #define LTSSM_SHIFT 24
106 #define LTSSM_MASK 0x3f
107 #define LTSSM_L0 0x10
108 #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
109
110 /* PCIe core controller registers */
111 #define CTRL_CORE_BASE_ADDR 0x18000
112 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
113 #define CTRL_MODE_SHIFT 0x0
114 #define CTRL_MODE_MASK 0x1
115 #define PCIE_CORE_MODE_DIRECT 0x0
116 #define PCIE_CORE_MODE_COMMAND 0x1
117
118 /* Transaction types */
119 #define PCIE_CONFIG_RD_TYPE0 0x8
120 #define PCIE_CONFIG_RD_TYPE1 0x9
121 #define PCIE_CONFIG_WR_TYPE0 0xa
122 #define PCIE_CONFIG_WR_TYPE1 0xb
123
124 /* PCI_BDF shifts 8bit, so we need extra 4bit shift */
125 #define PCIE_BDF(dev) (dev << 4)
126 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
127 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
128 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
129 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
130 #define PCIE_CONF_ADDR(bus, devfn, where) \
131 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
132 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
133
134 /* PCIe Retries & Timeout definitions */
135 #define MAX_RETRIES 10
136 #define PIO_WAIT_TIMEOUT 100
137 #define LINK_WAIT_TIMEOUT 100000
138
139 #define CFG_RD_UR_VAL 0xFFFFFFFF
140 #define CFG_RD_CRS_VAL 0xFFFF0001
141
142 /**
143 * struct pcie_advk - Advk PCIe controller state
144 *
145 * @reg_base: The base address of the register space.
146 * @first_busno: This driver supports multiple PCIe controllers.
147 * first_busno stores the bus number of the PCIe root-port
148 * number which may vary depending on the PCIe setup
149 * (PEX switches etc).
150 * @device: The pointer to PCI uclass device.
151 */
152 struct pcie_advk {
153 void *base;
154 int first_busno;
155 struct udevice *dev;
156 struct gpio_desc reset_gpio;
157 };
158
advk_writel(struct pcie_advk * pcie,uint val,uint reg)159 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
160 {
161 writel(val, pcie->base + reg);
162 }
163
advk_readl(struct pcie_advk * pcie,uint reg)164 static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
165 {
166 return readl(pcie->base + reg);
167 }
168
169 /**
170 * pcie_advk_addr_valid() - Check for valid bus address
171 *
172 * @bdf: The PCI device to access
173 * @first_busno: Bus number of the PCIe controller root complex
174 *
175 * Return: 1 on valid, 0 on invalid
176 */
pcie_advk_addr_valid(pci_dev_t bdf,int first_busno)177 static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
178 {
179 /*
180 * In PCIE-E only a single device (0) can exist
181 * on the local bus. Beyound the local bus, there might be
182 * a Switch and everything is possible.
183 */
184 if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
185 return 0;
186
187 return 1;
188 }
189
190 /**
191 * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
192 *
193 * @pcie: The PCI device to access
194 *
195 * Wait up to 1 micro second for PIO access to be accomplished.
196 *
197 * Return 1 (true) if PIO access is accomplished.
198 * Return 0 (false) if PIO access is timed out.
199 */
pcie_advk_wait_pio(struct pcie_advk * pcie)200 static int pcie_advk_wait_pio(struct pcie_advk *pcie)
201 {
202 uint start, isr;
203 uint count;
204
205 for (count = 0; count < MAX_RETRIES; count++) {
206 start = advk_readl(pcie, PIO_START);
207 isr = advk_readl(pcie, PIO_ISR);
208 if (!start && isr)
209 return 1;
210 /*
211 * Do not check the PIO state too frequently,
212 * 100us delay is appropriate.
213 */
214 udelay(PIO_WAIT_TIMEOUT);
215 }
216
217 dev_err(pcie->dev, "config read/write timed out\n");
218 return 0;
219 }
220
221 /**
222 * pcie_advk_check_pio_status() - Validate PIO status and get the read result
223 *
224 * @pcie: Pointer to the PCI bus
225 * @read: Read from or write to configuration space - true(read) false(write)
226 * @read_val: Pointer to the read result, only valid when read is true
227 *
228 */
pcie_advk_check_pio_status(struct pcie_advk * pcie,bool read,uint * read_val)229 static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
230 bool read,
231 uint *read_val)
232 {
233 uint reg;
234 unsigned int status;
235 char *strcomp_status, *str_posted;
236
237 reg = advk_readl(pcie, PIO_STAT);
238 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
239 PIO_COMPLETION_STATUS_SHIFT;
240
241 switch (status) {
242 case PIO_COMPLETION_STATUS_OK:
243 if (reg & PIO_ERR_STATUS) {
244 strcomp_status = "COMP_ERR";
245 break;
246 }
247 /* Get the read result */
248 if (read)
249 *read_val = advk_readl(pcie, PIO_RD_DATA);
250 /* No error */
251 strcomp_status = NULL;
252 break;
253 case PIO_COMPLETION_STATUS_UR:
254 if (read) {
255 /* For reading, UR is not an error status. */
256 *read_val = CFG_RD_UR_VAL;
257 strcomp_status = NULL;
258 } else {
259 strcomp_status = "UR";
260 }
261 break;
262 case PIO_COMPLETION_STATUS_CRS:
263 if (read) {
264 /* For reading, CRS is not an error status. */
265 *read_val = CFG_RD_CRS_VAL;
266 strcomp_status = NULL;
267 } else {
268 strcomp_status = "CRS";
269 }
270 break;
271 case PIO_COMPLETION_STATUS_CA:
272 strcomp_status = "CA";
273 break;
274 default:
275 strcomp_status = "Unknown";
276 break;
277 }
278
279 if (!strcomp_status)
280 return 0;
281
282 if (reg & PIO_NON_POSTED_REQ)
283 str_posted = "Non-posted";
284 else
285 str_posted = "Posted";
286
287 dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
288 str_posted, strcomp_status, reg,
289 advk_readl(pcie, PIO_ADDR_LS));
290
291 return -EFAULT;
292 }
293
294 /**
295 * pcie_advk_read_config() - Read from configuration space
296 *
297 * @bus: Pointer to the PCI bus
298 * @bdf: Identifies the PCIe device to access
299 * @offset: The offset into the device's configuration space
300 * @valuep: A pointer at which to store the read value
301 * @size: Indicates the size of access to perform
302 *
303 * Read a value of size @size from offset @offset within the configuration
304 * space of the device identified by the bus, device & function numbers in @bdf
305 * on the PCI bus @bus.
306 *
307 * Return: 0 on success
308 */
pcie_advk_read_config(const struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)309 static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
310 uint offset, ulong *valuep,
311 enum pci_size_t size)
312 {
313 struct pcie_advk *pcie = dev_get_priv(bus);
314 uint reg;
315 int ret;
316
317 dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
318 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
319
320 if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
321 dev_dbg(pcie->dev, "- out of range\n");
322 *valuep = pci_get_ff(size);
323 return 0;
324 }
325
326 /* Start PIO */
327 advk_writel(pcie, 0, PIO_START);
328 advk_writel(pcie, 1, PIO_ISR);
329
330 /* Program the control register */
331 reg = advk_readl(pcie, PIO_CTRL);
332 reg &= ~PIO_CTRL_TYPE_MASK;
333 if (PCI_BUS(bdf) == pcie->first_busno)
334 reg |= PCIE_CONFIG_RD_TYPE0;
335 else
336 reg |= PCIE_CONFIG_RD_TYPE1;
337 advk_writel(pcie, reg, PIO_CTRL);
338
339 /* Program the address registers */
340 reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
341 advk_writel(pcie, reg, PIO_ADDR_LS);
342 advk_writel(pcie, 0, PIO_ADDR_MS);
343
344 /* Start the transfer */
345 advk_writel(pcie, 1, PIO_START);
346
347 if (!pcie_advk_wait_pio(pcie))
348 return -EINVAL;
349
350 /* Check PIO status and get the read result */
351 ret = pcie_advk_check_pio_status(pcie, true, ®);
352 if (ret)
353 return ret;
354
355 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
356 offset, size, reg);
357 *valuep = pci_conv_32_to_size(reg, offset, size);
358
359 return 0;
360 }
361
362 /**
363 * pcie_calc_datastrobe() - Calculate data strobe
364 *
365 * @offset: The offset into the device's configuration space
366 * @size: Indicates the size of access to perform
367 *
368 * Calculate data strobe according to offset and size
369 *
370 */
pcie_calc_datastrobe(uint offset,enum pci_size_t size)371 static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
372 {
373 uint bytes, data_strobe;
374
375 switch (size) {
376 case PCI_SIZE_8:
377 bytes = 1;
378 break;
379 case PCI_SIZE_16:
380 bytes = 2;
381 break;
382 default:
383 bytes = 4;
384 }
385
386 data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
387
388 return data_strobe;
389 }
390
391 /**
392 * pcie_advk_write_config() - Write to configuration space
393 *
394 * @bus: Pointer to the PCI bus
395 * @bdf: Identifies the PCIe device to access
396 * @offset: The offset into the device's configuration space
397 * @value: The value to write
398 * @size: Indicates the size of access to perform
399 *
400 * Write the value @value of size @size from offset @offset within the
401 * configuration space of the device identified by the bus, device & function
402 * numbers in @bdf on the PCI bus @bus.
403 *
404 * Return: 0 on success
405 */
pcie_advk_write_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)406 static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
407 uint offset, ulong value,
408 enum pci_size_t size)
409 {
410 struct pcie_advk *pcie = dev_get_priv(bus);
411 uint reg;
412
413 dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
414 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
415 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
416 offset, size, value);
417
418 if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
419 dev_dbg(pcie->dev, "- out of range\n");
420 return 0;
421 }
422
423 /* Start PIO */
424 advk_writel(pcie, 0, PIO_START);
425 advk_writel(pcie, 1, PIO_ISR);
426
427 /* Program the control register */
428 reg = advk_readl(pcie, PIO_CTRL);
429 reg &= ~PIO_CTRL_TYPE_MASK;
430 if (PCI_BUS(bdf) == pcie->first_busno)
431 reg |= PCIE_CONFIG_WR_TYPE0;
432 else
433 reg |= PCIE_CONFIG_WR_TYPE1;
434 advk_writel(pcie, reg, PIO_CTRL);
435
436 /* Program the address registers */
437 reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
438 advk_writel(pcie, reg, PIO_ADDR_LS);
439 advk_writel(pcie, 0, PIO_ADDR_MS);
440 dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
441
442 /* Program the data register */
443 reg = pci_conv_size_to_32(0, value, offset, size);
444 advk_writel(pcie, reg, PIO_WR_DATA);
445 dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
446
447 /* Program the data strobe */
448 reg = pcie_calc_datastrobe(offset, size);
449 advk_writel(pcie, reg, PIO_WR_DATA_STRB);
450 dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
451
452 /* Start the transfer */
453 advk_writel(pcie, 1, PIO_START);
454
455 if (!pcie_advk_wait_pio(pcie)) {
456 return -EINVAL;
457 }
458
459 /* Check PIO status */
460 pcie_advk_check_pio_status(pcie, false, ®);
461
462 return 0;
463 }
464
465 /**
466 * pcie_advk_link_up() - Check if PCIe link is up or not
467 *
468 * @pcie: The PCI device to access
469 *
470 * Return 1 (true) on link up.
471 * Return 0 (false) on link down.
472 */
pcie_advk_link_up(struct pcie_advk * pcie)473 static int pcie_advk_link_up(struct pcie_advk *pcie)
474 {
475 u32 val, ltssm_state;
476
477 val = advk_readl(pcie, CFG_REG);
478 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
479 return ltssm_state >= LTSSM_L0;
480 }
481
482 /**
483 * pcie_advk_wait_for_link() - Wait for link training to be accomplished
484 *
485 * @pcie: The PCI device to access
486 *
487 * Wait up to 1 second for link training to be accomplished.
488 *
489 * Return 1 (true) if link training ends up with link up success.
490 * Return 0 (false) if link training ends up with link up failure.
491 */
pcie_advk_wait_for_link(struct pcie_advk * pcie)492 static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
493 {
494 int retries;
495
496 /* check if the link is up or not */
497 for (retries = 0; retries < MAX_RETRIES; retries++) {
498 if (pcie_advk_link_up(pcie)) {
499 printf("PCIE-%d: Link up\n", pcie->first_busno);
500 return 0;
501 }
502
503 udelay(LINK_WAIT_TIMEOUT);
504 }
505
506 printf("PCIE-%d: Link down\n", pcie->first_busno);
507
508 return -ETIMEDOUT;
509 }
510
511 /**
512 * pcie_advk_setup_hw() - PCIe initailzation
513 *
514 * @pcie: The PCI device to access
515 *
516 * Return: 0 on success
517 */
pcie_advk_setup_hw(struct pcie_advk * pcie)518 static int pcie_advk_setup_hw(struct pcie_advk *pcie)
519 {
520 u32 reg;
521
522 /* Set to Direct mode */
523 reg = advk_readl(pcie, CTRL_CONFIG_REG);
524 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
525 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
526 advk_writel(pcie, reg, CTRL_CONFIG_REG);
527
528 /* Set PCI global control register to RC mode */
529 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
530 reg |= (IS_RC_MSK << IS_RC_SHIFT);
531 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
532
533 /*
534 * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
535 * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor
536 * id in high 16 bits. Updating this register changes readback value of
537 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround
538 * for erratum 4.1: "The value of device and vendor ID is incorrect".
539 */
540 advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG);
541
542 /* Set Advanced Error Capabilities and Control PF0 register */
543 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
544 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
545 PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
546 PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
547 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
548
549 /* Set PCIe Device Control and Status 1 PF0 register */
550 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
551 (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE <<
552 PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT) |
553 (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE <<
554 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT) |
555 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
556 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
557
558 /* Program PCIe Control 2 to disable strict ordering */
559 reg = PCIE_CORE_CTRL2_RESERVED |
560 PCIE_CORE_CTRL2_TD_ENABLE;
561 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
562
563 /* Set GEN2 */
564 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
565 reg &= ~PCIE_GEN_SEL_MSK;
566 reg |= SPEED_GEN_2;
567 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
568
569 /* Set lane X1 */
570 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
571 reg &= ~LANE_CNT_MSK;
572 reg |= LANE_COUNT_1;
573 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
574
575 /* Enable link training */
576 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
577 reg |= LINK_TRAINING_EN;
578 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
579
580 /*
581 * Enable AXI address window location generation:
582 * When it is enabled, the default outbound window
583 * configurations (Default User Field: 0xD0074CFC)
584 * are used to transparent address translation for
585 * the outbound transactions. Thus, PCIe address
586 * windows are not required.
587 */
588 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
589 reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
590 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
591
592 /*
593 * Bypass the address window mapping for PIO:
594 * Since PIO access already contains all required
595 * info over AXI interface by PIO registers, the
596 * address window is not required.
597 */
598 reg = advk_readl(pcie, PIO_CTRL);
599 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
600 advk_writel(pcie, reg, PIO_CTRL);
601
602 /* Start link training */
603 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
604 reg |= PCIE_CORE_LINK_TRAINING;
605 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
606
607 /* Wait for PCIe link up */
608 if (pcie_advk_wait_for_link(pcie))
609 return -ENXIO;
610
611 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
612 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
613 PCIE_CORE_CMD_IO_ACCESS_EN |
614 PCIE_CORE_CMD_MEM_IO_REQ_EN;
615 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
616
617 return 0;
618 }
619
620 /**
621 * pcie_advk_probe() - Probe the PCIe bus for active link
622 *
623 * @dev: A pointer to the device being operated on
624 *
625 * Probe for an active link on the PCIe bus and configure the controller
626 * to enable this port.
627 *
628 * Return: 0 on success, else -ENODEV
629 */
pcie_advk_probe(struct udevice * dev)630 static int pcie_advk_probe(struct udevice *dev)
631 {
632 struct pcie_advk *pcie = dev_get_priv(dev);
633
634 gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio,
635 GPIOD_IS_OUT);
636 /*
637 * Issue reset to add-in card through the dedicated GPIO.
638 * Some boards are connecting the card reset pin to common system
639 * reset wire and others are using separate GPIO port.
640 * In the last case we have to release a reset of the addon card
641 * using this GPIO.
642 *
643 * FIX-ME:
644 * The PCIe RESET signal is not supposed to be released along
645 * with the SOC RESET signal. It should be lowered as early as
646 * possible before PCIe PHY initialization. Moreover, the PCIe
647 * clock should be gated as well.
648 */
649 if (dm_gpio_is_valid(&pcie->reset_gpio)) {
650 dev_dbg(dev, "Toggle PCIE Reset GPIO ...\n");
651 dm_gpio_set_value(&pcie->reset_gpio, 1);
652 mdelay(200);
653 dm_gpio_set_value(&pcie->reset_gpio, 0);
654 } else {
655 dev_warn(dev, "PCIE Reset on GPIO support is missing\n");
656 }
657
658 pcie->first_busno = dev_seq(dev);
659 pcie->dev = pci_get_controller(dev);
660
661 return pcie_advk_setup_hw(pcie);
662 }
663
pcie_advk_remove(struct udevice * dev)664 static int pcie_advk_remove(struct udevice *dev)
665 {
666 struct pcie_advk *pcie = dev_get_priv(dev);
667 u32 reg;
668
669 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
670 reg &= ~LINK_TRAINING_EN;
671 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
672
673 return 0;
674 }
675
676 /**
677 * pcie_advk_of_to_plat() - Translate from DT to device state
678 *
679 * @dev: A pointer to the device being operated on
680 *
681 * Translate relevant data from the device tree pertaining to device @dev into
682 * state that the driver will later make use of. This state is stored in the
683 * device's private data structure.
684 *
685 * Return: 0 on success, else -EINVAL
686 */
pcie_advk_of_to_plat(struct udevice * dev)687 static int pcie_advk_of_to_plat(struct udevice *dev)
688 {
689 struct pcie_advk *pcie = dev_get_priv(dev);
690
691 /* Get the register base address */
692 pcie->base = (void *)dev_read_addr_index(dev, 0);
693 if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
694 return -EINVAL;
695
696 return 0;
697 }
698
699 static const struct dm_pci_ops pcie_advk_ops = {
700 .read_config = pcie_advk_read_config,
701 .write_config = pcie_advk_write_config,
702 };
703
704 static const struct udevice_id pcie_advk_ids[] = {
705 { .compatible = "marvell,armada-37xx-pcie" },
706 { }
707 };
708
709 U_BOOT_DRIVER(pcie_advk) = {
710 .name = "pcie_advk",
711 .id = UCLASS_PCI,
712 .of_match = pcie_advk_ids,
713 .ops = &pcie_advk_ops,
714 .of_to_plat = pcie_advk_of_to_plat,
715 .probe = pcie_advk_probe,
716 .remove = pcie_advk_remove,
717 .flags = DM_FLAG_OS_PREPARE,
718 .priv_auto = sizeof(struct pcie_advk),
719 };
720