1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Meson AXG MIPI DPHY driver
4 *
5 * Copyright (C) 2018 Amlogic, Inc. All rights reserved
6 * Copyright (C) 2020 BayLibre, SAS
7 * Author: Neil Armstrong <narmstrong@baylibre.com>
8 */
9
10 #include <common.h>
11 #include <log.h>
12 #include <malloc.h>
13 #include <asm/io.h>
14 #include <bitfield.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <generic-phy.h>
18 #include <regmap.h>
19 #include <linux/delay.h>
20 #include <power/regulator.h>
21 #include <reset.h>
22 #include <clk.h>
23 #include <phy-mipi-dphy.h>
24
25 #include <linux/bitops.h>
26 #include <linux/compat.h>
27 #include <linux/bitfield.h>
28
29 /* [31] soft reset for the phy.
30 * 1: reset. 0: dessert the reset.
31 * [30] clock lane soft reset.
32 * [29] data byte lane 3 soft reset.
33 * [28] data byte lane 2 soft reset.
34 * [27] data byte lane 1 soft reset.
35 * [26] data byte lane 0 soft reset.
36 * [25] mipi dsi pll clock selection.
37 * 1: clock from fixed 850Mhz clock source. 0: from VID2 PLL.
38 * [12] mipi HSbyteclk enable.
39 * [11] mipi divider clk selection.
40 * 1: select the mipi DDRCLKHS from clock divider.
41 * 0: from PLL clock.
42 * [10] mipi clock divider control.
43 * 1: /4. 0: /2.
44 * [9] mipi divider output enable.
45 * [8] mipi divider counter enable.
46 * [7] PLL clock enable.
47 * [5] LPDT data endian.
48 * 1 = transfer the high bit first. 0 : transfer the low bit first.
49 * [4] HS data endian.
50 * [3] force data byte lane in stop mode.
51 * [2] force data byte lane 0 in receiver mode.
52 * [1] write 1 to sync the txclkesc input. the internal logic have to
53 * use txclkesc to decide Txvalid and Txready.
54 * [0] enalbe the MIPI DPHY TxDDRClk.
55 */
56 #define MIPI_DSI_PHY_CTRL 0x0
57
58 /* [31] clk lane tx_hs_en control selection.
59 * 1: from register. 0: use clk lane state machine.
60 * [30] register bit for clock lane tx_hs_en.
61 * [29] clk lane tx_lp_en contrl selection.
62 * 1: from register. 0: from clk lane state machine.
63 * [28] register bit for clock lane tx_lp_en.
64 * [27] chan0 tx_hs_en control selection.
65 * 1: from register. 0: from chan0 state machine.
66 * [26] register bit for chan0 tx_hs_en.
67 * [25] chan0 tx_lp_en control selection.
68 * 1: from register. 0: from chan0 state machine.
69 * [24] register bit from chan0 tx_lp_en.
70 * [23] chan0 rx_lp_en control selection.
71 * 1: from register. 0: from chan0 state machine.
72 * [22] register bit from chan0 rx_lp_en.
73 * [21] chan0 contention detection enable control selection.
74 * 1: from register. 0: from chan0 state machine.
75 * [20] register bit from chan0 contention dectection enable.
76 * [19] chan1 tx_hs_en control selection.
77 * 1: from register. 0: from chan0 state machine.
78 * [18] register bit for chan1 tx_hs_en.
79 * [17] chan1 tx_lp_en control selection.
80 * 1: from register. 0: from chan0 state machine.
81 * [16] register bit from chan1 tx_lp_en.
82 * [15] chan2 tx_hs_en control selection.
83 * 1: from register. 0: from chan0 state machine.
84 * [14] register bit for chan2 tx_hs_en.
85 * [13] chan2 tx_lp_en control selection.
86 * 1: from register. 0: from chan0 state machine.
87 * [12] register bit from chan2 tx_lp_en.
88 * [11] chan3 tx_hs_en control selection.
89 * 1: from register. 0: from chan0 state machine.
90 * [10] register bit for chan3 tx_hs_en.
91 * [9] chan3 tx_lp_en control selection.
92 * 1: from register. 0: from chan0 state machine.
93 * [8] register bit from chan3 tx_lp_en.
94 * [4] clk chan power down. this bit is also used as the power down
95 * of the whole MIPI_DSI_PHY.
96 * [3] chan3 power down.
97 * [2] chan2 power down.
98 * [1] chan1 power down.
99 * [0] chan0 power down.
100 */
101 #define MIPI_DSI_CHAN_CTRL 0x4
102
103 /* [24] rx turn watch dog triggered.
104 * [23] rx esc watchdog triggered.
105 * [22] mbias ready.
106 * [21] txclkesc synced and ready.
107 * [20:17] clk lane state. {mbias_ready, tx_stop, tx_ulps, tx_hs_active}
108 * [16:13] chan3 state{0, tx_stop, tx_ulps, tx_hs_active}
109 * [12:9] chan2 state.{0, tx_stop, tx_ulps, tx_hs_active}
110 * [8:5] chan1 state. {0, tx_stop, tx_ulps, tx_hs_active}
111 * [4:0] chan0 state. {TX_STOP, tx_ULPS, hs_active, direction, rxulpsesc}
112 */
113 #define MIPI_DSI_CHAN_STS 0x8
114
115 /* [31:24] TCLK_PREPARE.
116 * [23:16] TCLK_ZERO.
117 * [15:8] TCLK_POST.
118 * [7:0] TCLK_TRAIL.
119 */
120 #define MIPI_DSI_CLK_TIM 0xc
121
122 /* [31:24] THS_PREPARE.
123 * [23:16] THS_ZERO.
124 * [15:8] THS_TRAIL.
125 * [7:0] THS_EXIT.
126 */
127 #define MIPI_DSI_HS_TIM 0x10
128
129 /* [31:24] tTA_GET.
130 * [23:16] tTA_GO.
131 * [15:8] tTA_SURE.
132 * [7:0] tLPX.
133 */
134 #define MIPI_DSI_LP_TIM 0x14
135
136 /* wait time to MIPI DIS analog ready. */
137 #define MIPI_DSI_ANA_UP_TIM 0x18
138
139 /* TINIT. */
140 #define MIPI_DSI_INIT_TIM 0x1c
141
142 /* TWAKEUP. */
143 #define MIPI_DSI_WAKEUP_TIM 0x20
144
145 /* when in RxULPS check state, after the the logic enable the analog,
146 * how long we should wait to check the lP state .
147 */
148 #define MIPI_DSI_LPOK_TIM 0x24
149
150 /* Watchdog for RX low power state no finished. */
151 #define MIPI_DSI_LP_WCHDOG 0x28
152
153 /* tMBIAS, after send power up signals to analog,
154 * how long we should wait for analog powered up.
155 */
156 #define MIPI_DSI_ANA_CTRL 0x2c
157
158 /* [31:8] reserved for future.
159 * [7:0] tCLK_PRE.
160 */
161 #define MIPI_DSI_CLK_TIM1 0x30
162
163 /* watchdog for turn around waiting time. */
164 #define MIPI_DSI_TURN_WCHDOG 0x34
165
166 /* When in RxULPS state, how frequency we should to check
167 * if the TX side out of ULPS state.
168 */
169 #define MIPI_DSI_ULPS_CHECK 0x38
170 #define MIPI_DSI_TEST_CTRL0 0x3c
171 #define MIPI_DSI_TEST_CTRL1 0x40
172
173 #define NSEC_PER_MSEC 1000000L
174
175 struct phy_meson_axg_mipi_dphy_priv {
176 struct regmap *regmap;
177 #if CONFIG_IS_ENABLED(CLK)
178 struct clk clk;
179 #endif
180 struct reset_ctl reset;
181 struct phy analog;
182 struct phy_configure_opts_mipi_dphy config;
183 };
184
phy_meson_axg_mipi_dphy_configure(struct phy * phy,void * params)185 static int phy_meson_axg_mipi_dphy_configure(struct phy *phy, void *params)
186 {
187 struct udevice *dev = phy->dev;
188 struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
189 struct phy_configure_opts_mipi_dphy *config = params;
190 int ret;
191
192 ret = phy_mipi_dphy_config_validate(config);
193 if (ret)
194 return ret;
195
196 ret = generic_phy_configure(&priv->analog, config);
197 if (ret)
198 return ret;
199
200 memcpy(&priv->config, config, sizeof(priv->config));
201
202 return 0;
203 }
204
phy_meson_axg_mipi_dphy_power_on(struct phy * phy)205 static int phy_meson_axg_mipi_dphy_power_on(struct phy *phy)
206 {
207 struct udevice *dev = phy->dev;
208 struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
209 unsigned long temp;
210 int ret;
211
212 ret = generic_phy_power_on(&priv->analog);
213 if (ret)
214 return ret;
215
216 /* enable phy clock */
217 regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, 0x1);
218 regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL,
219 BIT(0) | /* enable the DSI PLL clock . */
220 BIT(7) | /* enable pll clock which connected to DDR clock path */
221 BIT(8)); /* enable the clock divider counter */
222
223 /* enable the divider clock out */
224 regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(9), BIT(9));
225
226 /* enable the byte clock generation. */
227 regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(12), BIT(12));
228 regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), BIT(31));
229 regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), 0);
230
231 /* Calculate lanebyteclk period in ps */
232 temp = (1000000 * 100) / (priv->config.hs_clk_rate / 1000);
233 temp = temp * 8 * 10;
234
235 regmap_write(priv->regmap, MIPI_DSI_CLK_TIM,
236 DIV_ROUND_UP(priv->config.clk_trail, temp) |
237 (DIV_ROUND_UP(priv->config.clk_post +
238 priv->config.hs_trail, temp) << 8) |
239 (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) |
240 (DIV_ROUND_UP(priv->config.clk_prepare, temp) << 24));
241 regmap_write(priv->regmap, MIPI_DSI_CLK_TIM1,
242 DIV_ROUND_UP(priv->config.clk_pre, temp));
243
244 regmap_write(priv->regmap, MIPI_DSI_HS_TIM,
245 DIV_ROUND_UP(priv->config.hs_exit, temp) |
246 (DIV_ROUND_UP(priv->config.hs_trail, temp) << 8) |
247 (DIV_ROUND_UP(priv->config.hs_zero, temp) << 16) |
248 (DIV_ROUND_UP(priv->config.hs_prepare, temp) << 24));
249
250 regmap_write(priv->regmap, MIPI_DSI_LP_TIM,
251 DIV_ROUND_UP(priv->config.lpx, temp) |
252 (DIV_ROUND_UP(priv->config.ta_sure, temp) << 8) |
253 (DIV_ROUND_UP(priv->config.ta_go, temp) << 16) |
254 (DIV_ROUND_UP(priv->config.ta_get, temp) << 24));
255
256 regmap_write(priv->regmap, MIPI_DSI_ANA_UP_TIM, 0x0100);
257 regmap_write(priv->regmap, MIPI_DSI_INIT_TIM,
258 DIV_ROUND_UP(priv->config.init * NSEC_PER_MSEC, temp));
259 regmap_write(priv->regmap, MIPI_DSI_WAKEUP_TIM,
260 DIV_ROUND_UP(priv->config.wakeup * NSEC_PER_MSEC, temp));
261 regmap_write(priv->regmap, MIPI_DSI_LPOK_TIM, 0x7C);
262 regmap_write(priv->regmap, MIPI_DSI_ULPS_CHECK, 0x927C);
263 regmap_write(priv->regmap, MIPI_DSI_LP_WCHDOG, 0x1000);
264 regmap_write(priv->regmap, MIPI_DSI_TURN_WCHDOG, 0x1000);
265
266 /* Powerup the analog circuit */
267 switch (priv->config.lanes) {
268 case 1:
269 regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xe);
270 break;
271 case 2:
272 regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xc);
273 break;
274 case 3:
275 regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0x8);
276 break;
277 case 4:
278 default:
279 regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0);
280 break;
281 }
282
283 /* Trigger a sync active for esc_clk */
284 regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(1), BIT(1));
285
286 return 0;
287 }
288
phy_meson_axg_mipi_dphy_power_off(struct phy * phy)289 static int phy_meson_axg_mipi_dphy_power_off(struct phy *phy)
290 {
291 struct udevice *dev = phy->dev;
292 struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
293
294 regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xf);
295 regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31));
296
297 return generic_phy_power_off(&priv->analog);
298 }
299
phy_meson_axg_mipi_dphy_init(struct phy * phy)300 static int phy_meson_axg_mipi_dphy_init(struct phy *phy)
301 {
302 struct udevice *dev = phy->dev;
303 struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
304 int ret;
305
306 ret = generic_phy_init(&priv->analog);
307 if (ret)
308 return ret;
309
310 ret = reset_assert(&priv->reset);
311 udelay(1);
312 ret |= reset_deassert(&priv->reset);
313 if (ret)
314 return ret;
315
316 return 0;
317 }
318
phy_meson_axg_mipi_dphy_exit(struct phy * phy)319 static int phy_meson_axg_mipi_dphy_exit(struct phy *phy)
320 {
321 struct udevice *dev = phy->dev;
322 struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
323 int ret;
324
325 ret = generic_phy_exit(&priv->analog);
326 if (ret)
327 return ret;
328
329 return reset_assert(&priv->reset);
330 }
331
332 struct phy_ops meson_axg_mipi_dphy_ops = {
333 .init = phy_meson_axg_mipi_dphy_init,
334 .exit = phy_meson_axg_mipi_dphy_exit,
335 .power_on = phy_meson_axg_mipi_dphy_power_on,
336 .power_off = phy_meson_axg_mipi_dphy_power_off,
337 .configure = phy_meson_axg_mipi_dphy_configure,
338 };
339
meson_axg_mipi_dphy_probe(struct udevice * dev)340 int meson_axg_mipi_dphy_probe(struct udevice *dev)
341 {
342 struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
343 int ret;
344
345 ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
346 if (ret)
347 return ret;
348
349 ret = generic_phy_get_by_index(dev, 0, &priv->analog);
350 if (ret)
351 return ret;
352
353 ret = reset_get_by_index(dev, 0, &priv->reset);
354 if (ret == -ENOTSUPP)
355 return 0;
356 else if (ret)
357 return ret;
358
359 ret = reset_deassert(&priv->reset);
360 if (ret) {
361 reset_release_all(&priv->reset, 1);
362 return ret;
363 }
364
365 #if CONFIG_IS_ENABLED(CLK)
366 ret = clk_get_by_index(dev, 0, &priv->clk);
367 if (ret < 0)
368 return ret;
369
370 ret = clk_enable(&priv->clk);
371 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
372 pr_err("failed to enable PHY clock\n");
373 clk_free(&priv->clk);
374 return ret;
375 }
376 #endif
377
378 return 0;
379 }
380
381 static const struct udevice_id meson_axg_mipi_dphy_ids[] = {
382 { .compatible = "amlogic,axg-mipi-dphy" },
383 { }
384 };
385
386 U_BOOT_DRIVER(meson_axg_mipi_dphy) = {
387 .name = "meson_axg_mipi_dphy",
388 .id = UCLASS_PHY,
389 .of_match = meson_axg_mipi_dphy_ids,
390 .probe = meson_axg_mipi_dphy_probe,
391 .ops = &meson_axg_mipi_dphy_ops,
392 .priv_auto_alloc_size = sizeof(struct phy_meson_axg_mipi_dphy_priv),
393 };
394