1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <log.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <dm/pinctrl.h>
13 #include <mach/ar71xx_regs.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 enum periph_id {
18 PERIPH_ID_UART0,
19 PERIPH_ID_SPI0,
20 PERIPH_ID_NONE = -1,
21 };
22
23 struct ar933x_pinctrl_priv {
24 void __iomem *regs;
25 };
26
pinctrl_ar933x_spi_config(struct ar933x_pinctrl_priv * priv,int cs)27 static void pinctrl_ar933x_spi_config(struct ar933x_pinctrl_priv *priv, int cs)
28 {
29 switch (cs) {
30 case 0:
31 clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
32 AR933X_GPIO(4), AR933X_GPIO(3) |
33 AR933X_GPIO(5) | AR933X_GPIO(2));
34 setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
35 AR933X_GPIO_FUNC_SPI_EN |
36 AR933X_GPIO_FUNC_RES_TRUE);
37 break;
38 }
39 }
40
pinctrl_ar933x_uart_config(struct ar933x_pinctrl_priv * priv,int uart_id)41 static void pinctrl_ar933x_uart_config(struct ar933x_pinctrl_priv *priv, int uart_id)
42 {
43 switch (uart_id) {
44 case PERIPH_ID_UART0:
45 clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
46 AR933X_GPIO(9), AR933X_GPIO(10));
47 setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
48 AR933X_GPIO_FUNC_UART_EN |
49 AR933X_GPIO_FUNC_RES_TRUE);
50 break;
51 }
52 }
53
ar933x_pinctrl_request(struct udevice * dev,int func,int flags)54 static int ar933x_pinctrl_request(struct udevice *dev, int func, int flags)
55 {
56 struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
57
58 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
59 switch (func) {
60 case PERIPH_ID_SPI0:
61 pinctrl_ar933x_spi_config(priv, flags);
62 break;
63 case PERIPH_ID_UART0:
64 pinctrl_ar933x_uart_config(priv, func);
65 break;
66 default:
67 return -EINVAL;
68 }
69
70 return 0;
71 }
72
ar933x_pinctrl_get_periph_id(struct udevice * dev,struct udevice * periph)73 static int ar933x_pinctrl_get_periph_id(struct udevice *dev,
74 struct udevice *periph)
75 {
76 u32 cell[2];
77 int ret;
78
79 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
80 "interrupts", cell, ARRAY_SIZE(cell));
81 if (ret < 0)
82 return -EINVAL;
83
84 switch (cell[0]) {
85 case 128:
86 return PERIPH_ID_UART0;
87 case 129:
88 return PERIPH_ID_SPI0;
89 }
90 return -ENOENT;
91 }
92
ar933x_pinctrl_set_state_simple(struct udevice * dev,struct udevice * periph)93 static int ar933x_pinctrl_set_state_simple(struct udevice *dev,
94 struct udevice *periph)
95 {
96 int func;
97
98 func = ar933x_pinctrl_get_periph_id(dev, periph);
99 if (func < 0)
100 return func;
101 return ar933x_pinctrl_request(dev, func, 0);
102 }
103
104 static struct pinctrl_ops ar933x_pinctrl_ops = {
105 .set_state_simple = ar933x_pinctrl_set_state_simple,
106 .request = ar933x_pinctrl_request,
107 .get_periph_id = ar933x_pinctrl_get_periph_id,
108 };
109
ar933x_pinctrl_probe(struct udevice * dev)110 static int ar933x_pinctrl_probe(struct udevice *dev)
111 {
112 struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
113 fdt_addr_t addr;
114
115 addr = dev_read_addr(dev);
116 if (addr == FDT_ADDR_T_NONE)
117 return -EINVAL;
118
119 priv->regs = map_physmem(addr,
120 AR71XX_GPIO_SIZE,
121 MAP_NOCACHE);
122 return 0;
123 }
124
125 static const struct udevice_id ar933x_pinctrl_ids[] = {
126 { .compatible = "qca,ar933x-pinctrl" },
127 { }
128 };
129
130 U_BOOT_DRIVER(pinctrl_ar933x) = {
131 .name = "pinctrl_ar933x",
132 .id = UCLASS_PINCTRL,
133 .of_match = ar933x_pinctrl_ids,
134 .priv_auto = sizeof(struct ar933x_pinctrl_priv),
135 .ops = &ar933x_pinctrl_ops,
136 .probe = ar933x_pinctrl_probe,
137 };
138