1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Pinctrl driver for Microchip PIC32 SoCs
4 * Copyright (c) 2015 Microchip Technology Inc.
5 * Written by Purna Chandra Mandal <purna.mandal@microchip.com>
6 */
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <log.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <dm/pinctrl.h>
14 #include <linux/bitops.h>
15 #include <mach/pic32.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 /* PIC32 has 10 peripheral ports with 16 pins each.
20 * Ports are marked PORTA-PORTK or PORT0-PORT9.
21 */
22 enum {
23 PIC32_PORT_A = 0,
24 PIC32_PORT_B = 1,
25 PIC32_PORT_C = 2,
26 PIC32_PORT_D = 3,
27 PIC32_PORT_E = 4,
28 PIC32_PORT_F = 5,
29 PIC32_PORT_G = 6,
30 PIC32_PORT_H = 7,
31 PIC32_PORT_J = 8, /* no PORT_I */
32 PIC32_PORT_K = 9,
33 PIC32_PINS_PER_PORT = 16,
34 };
35
36 #define PIN_CONFIG_PIC32_DIGITAL (PIN_CONFIG_END + 1)
37 #define PIN_CONFIG_PIC32_ANALOG (PIN_CONFIG_END + 2)
38
39 /* pin configuration descriptor */
40 struct pic32_pin_config {
41 u16 port; /* port number */
42 u16 pin; /* pin number in the port */
43 u32 config; /* one of PIN_CONFIG_* */
44 };
45 #define PIN_CONFIG(_prt, _pin, _cfg) \
46 {.port = (_prt), .pin = (_pin), .config = (_cfg), }
47
48 /* In PIC32 muxing is performed at pin-level through two
49 * different set of registers - one set for input functions,
50 * and other for output functions.
51 * Pin configuration is handled through port register.
52 */
53 /* Port control registers */
54 struct pic32_reg_port {
55 struct pic32_reg_atomic ansel;
56 struct pic32_reg_atomic tris;
57 struct pic32_reg_atomic port;
58 struct pic32_reg_atomic lat;
59 struct pic32_reg_atomic odc;
60 struct pic32_reg_atomic cnpu;
61 struct pic32_reg_atomic cnpd;
62 struct pic32_reg_atomic cncon;
63 struct pic32_reg_atomic unused[8];
64 };
65
66 /* Input function mux registers */
67 struct pic32_reg_in_mux {
68 u32 unused0;
69 u32 int1[4];
70 u32 unused1;
71 u32 t2ck[8];
72 u32 ic1[9];
73 u32 unused2;
74 u32 ocfar;
75 u32 unused3;
76 u32 u1rx;
77 u32 u1cts;
78 u32 u2rx;
79 u32 u2cts;
80 u32 u3rx;
81 u32 u3cts;
82 u32 u4rx;
83 u32 u4cts;
84 u32 u5rx;
85 u32 u5cts;
86 u32 u6rx;
87 u32 u6cts;
88 u32 unused4;
89 u32 sdi1;
90 u32 ss1;
91 u32 unused5;
92 u32 sdi2;
93 u32 ss2;
94 u32 unused6;
95 u32 sdi3;
96 u32 ss3;
97 u32 unused7;
98 u32 sdi4;
99 u32 ss4;
100 u32 unused8;
101 u32 sdi5;
102 u32 ss5;
103 u32 unused9;
104 u32 sdi6;
105 u32 ss6;
106 u32 c1rx;
107 u32 c2rx;
108 u32 refclki1;
109 u32 refclki2;
110 u32 refclki3;
111 u32 refclki4;
112 };
113
114 /* output mux register offset */
115 #define PPS_OUT(__port, __pin) \
116 (((__port) * PIC32_PINS_PER_PORT + (__pin)) << 2)
117
118
119 struct pic32_pinctrl_priv {
120 struct pic32_reg_in_mux *mux_in; /* mux input function */
121 struct pic32_reg_port *pinconf; /* pin configuration*/
122 void __iomem *mux_out; /* mux output function */
123 };
124
125 enum {
126 PERIPH_ID_UART1,
127 PERIPH_ID_UART2,
128 PERIPH_ID_ETH,
129 PERIPH_ID_USB,
130 PERIPH_ID_SDHCI,
131 PERIPH_ID_I2C1,
132 PERIPH_ID_I2C2,
133 PERIPH_ID_SPI1,
134 PERIPH_ID_SPI2,
135 PERIPH_ID_SQI,
136 };
137
pic32_pinconfig_one(struct pic32_pinctrl_priv * priv,u32 port_nr,u32 pin,u32 param)138 static int pic32_pinconfig_one(struct pic32_pinctrl_priv *priv,
139 u32 port_nr, u32 pin, u32 param)
140 {
141 struct pic32_reg_port *port;
142
143 port = &priv->pinconf[port_nr];
144 switch (param) {
145 case PIN_CONFIG_PIC32_DIGITAL:
146 writel(BIT(pin), &port->ansel.clr);
147 break;
148 case PIN_CONFIG_PIC32_ANALOG:
149 writel(BIT(pin), &port->ansel.set);
150 break;
151 case PIN_CONFIG_INPUT_ENABLE:
152 writel(BIT(pin), &port->tris.set);
153 break;
154 case PIN_CONFIG_OUTPUT:
155 writel(BIT(pin), &port->tris.clr);
156 break;
157 case PIN_CONFIG_BIAS_PULL_UP:
158 writel(BIT(pin), &port->cnpu.set);
159 break;
160 case PIN_CONFIG_BIAS_PULL_DOWN:
161 writel(BIT(pin), &port->cnpd.set);
162 break;
163 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
164 writel(BIT(pin), &port->odc.set);
165 break;
166 default:
167 break;
168 }
169
170 return 0;
171 }
172
pic32_pinconfig_set(struct pic32_pinctrl_priv * priv,const struct pic32_pin_config * list,int count)173 static int pic32_pinconfig_set(struct pic32_pinctrl_priv *priv,
174 const struct pic32_pin_config *list, int count)
175 {
176 int i;
177
178 for (i = 0 ; i < count; i++)
179 pic32_pinconfig_one(priv, list[i].port,
180 list[i].pin, list[i].config);
181
182 return 0;
183 }
184
pic32_eth_pin_config(struct udevice * dev)185 static void pic32_eth_pin_config(struct udevice *dev)
186 {
187 struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
188 const struct pic32_pin_config configs[] = {
189 /* EMDC - D11 */
190 PIN_CONFIG(PIC32_PORT_D, 11, PIN_CONFIG_PIC32_DIGITAL),
191 PIN_CONFIG(PIC32_PORT_D, 11, PIN_CONFIG_OUTPUT),
192 /* ETXEN */
193 PIN_CONFIG(PIC32_PORT_D, 6, PIN_CONFIG_PIC32_DIGITAL),
194 PIN_CONFIG(PIC32_PORT_D, 6, PIN_CONFIG_OUTPUT),
195 /* ECRSDV */
196 PIN_CONFIG(PIC32_PORT_H, 13, PIN_CONFIG_PIC32_DIGITAL),
197 PIN_CONFIG(PIC32_PORT_H, 13, PIN_CONFIG_INPUT_ENABLE),
198 /* ERXD0 */
199 PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_PIC32_DIGITAL),
200 PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_INPUT_ENABLE),
201 PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_BIAS_PULL_DOWN),
202 /* ERXD1 */
203 PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_PIC32_DIGITAL),
204 PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_INPUT_ENABLE),
205 PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_BIAS_PULL_DOWN),
206 /* EREFCLK */
207 PIN_CONFIG(PIC32_PORT_J, 11, PIN_CONFIG_PIC32_DIGITAL),
208 PIN_CONFIG(PIC32_PORT_J, 11, PIN_CONFIG_INPUT_ENABLE),
209 /* ETXD1 */
210 PIN_CONFIG(PIC32_PORT_J, 9, PIN_CONFIG_PIC32_DIGITAL),
211 PIN_CONFIG(PIC32_PORT_J, 9, PIN_CONFIG_OUTPUT),
212 /* ETXD0 */
213 PIN_CONFIG(PIC32_PORT_J, 8, PIN_CONFIG_PIC32_DIGITAL),
214 PIN_CONFIG(PIC32_PORT_J, 8, PIN_CONFIG_OUTPUT),
215 /* EMDIO */
216 PIN_CONFIG(PIC32_PORT_J, 1, PIN_CONFIG_PIC32_DIGITAL),
217 PIN_CONFIG(PIC32_PORT_J, 1, PIN_CONFIG_INPUT_ENABLE),
218 /* ERXERR */
219 PIN_CONFIG(PIC32_PORT_F, 3, PIN_CONFIG_PIC32_DIGITAL),
220 PIN_CONFIG(PIC32_PORT_F, 3, PIN_CONFIG_INPUT_ENABLE),
221 };
222
223 pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
224 }
225
pic32_sdhci_pin_config(struct udevice * dev)226 static void pic32_sdhci_pin_config(struct udevice *dev)
227 {
228 struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
229 const struct pic32_pin_config configs[] = {
230 /* SDWP - H2 */
231 PIN_CONFIG(PIC32_PORT_H, 2, PIN_CONFIG_PIC32_DIGITAL),
232 /* SDCD - A0 */
233 PIN_CONFIG(PIC32_PORT_A, 0, PIN_CONFIG_PIC32_DIGITAL),
234 /* SDCMD - D4 */
235 PIN_CONFIG(PIC32_PORT_D, 4, PIN_CONFIG_PIC32_DIGITAL),
236 /* SDCK - A6 */
237 PIN_CONFIG(PIC32_PORT_A, 6, PIN_CONFIG_PIC32_DIGITAL),
238 /* SDDATA0 - G13 */
239 PIN_CONFIG(PIC32_PORT_G, 13, PIN_CONFIG_PIC32_DIGITAL),
240 /* SDDATA1 - G12 */
241 PIN_CONFIG(PIC32_PORT_G, 12, PIN_CONFIG_PIC32_DIGITAL),
242 /* SDDATA2 - G14 */
243 PIN_CONFIG(PIC32_PORT_G, 14, PIN_CONFIG_PIC32_DIGITAL),
244 /* SDDATA3 - A7 */
245 PIN_CONFIG(PIC32_PORT_A, 7, PIN_CONFIG_PIC32_DIGITAL),
246 };
247
248 pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
249 }
250
pic32_pinctrl_request(struct udevice * dev,int func,int flags)251 static int pic32_pinctrl_request(struct udevice *dev, int func, int flags)
252 {
253 struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
254
255 switch (func) {
256 case PERIPH_ID_UART2:
257 /* PPS for U2 RX/TX */
258 writel(0x02, priv->mux_out + PPS_OUT(PIC32_PORT_G, 9));
259 writel(0x05, &priv->mux_in->u2rx); /* B0 */
260 /* set digital mode */
261 pic32_pinconfig_one(priv, PIC32_PORT_G, 9,
262 PIN_CONFIG_PIC32_DIGITAL);
263 pic32_pinconfig_one(priv, PIC32_PORT_B, 0,
264 PIN_CONFIG_PIC32_DIGITAL);
265 break;
266 case PERIPH_ID_ETH:
267 pic32_eth_pin_config(dev);
268 break;
269 case PERIPH_ID_SDHCI:
270 pic32_sdhci_pin_config(dev);
271 break;
272 default:
273 debug("%s: unknown-unhandled case\n", __func__);
274 break;
275 }
276
277 return 0;
278 }
279
pic32_pinctrl_get_periph_id(struct udevice * dev,struct udevice * periph)280 static int pic32_pinctrl_get_periph_id(struct udevice *dev,
281 struct udevice *periph)
282 {
283 int ret;
284 u32 cell[2];
285
286 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
287 "interrupts", cell, ARRAY_SIZE(cell));
288 if (ret < 0)
289 return -EINVAL;
290
291 /* interrupt number */
292 switch (cell[0]) {
293 case 112 ... 114:
294 return PERIPH_ID_UART1;
295 case 145 ... 147:
296 return PERIPH_ID_UART2;
297 case 109 ... 111:
298 return PERIPH_ID_SPI1;
299 case 142 ... 144:
300 return PERIPH_ID_SPI2;
301 case 115 ... 117:
302 return PERIPH_ID_I2C1;
303 case 148 ... 150:
304 return PERIPH_ID_I2C2;
305 case 132 ... 133:
306 return PERIPH_ID_USB;
307 case 169:
308 return PERIPH_ID_SQI;
309 case 191:
310 return PERIPH_ID_SDHCI;
311 case 153:
312 return PERIPH_ID_ETH;
313 default:
314 break;
315 }
316
317 return -ENOENT;
318 }
319
pic32_pinctrl_set_state_simple(struct udevice * dev,struct udevice * periph)320 static int pic32_pinctrl_set_state_simple(struct udevice *dev,
321 struct udevice *periph)
322 {
323 int func;
324
325 debug("%s: periph %s\n", __func__, periph->name);
326 func = pic32_pinctrl_get_periph_id(dev, periph);
327 if (func < 0)
328 return func;
329 return pic32_pinctrl_request(dev, func, 0);
330 }
331
332 static struct pinctrl_ops pic32_pinctrl_ops = {
333 .set_state_simple = pic32_pinctrl_set_state_simple,
334 .request = pic32_pinctrl_request,
335 .get_periph_id = pic32_pinctrl_get_periph_id,
336 };
337
pic32_pinctrl_probe(struct udevice * dev)338 static int pic32_pinctrl_probe(struct udevice *dev)
339 {
340 struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
341 struct fdt_resource res;
342 void *fdt = (void *)gd->fdt_blob;
343 int node = dev_of_offset(dev);
344 int ret;
345
346 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
347 "ppsin", &res);
348 if (ret < 0) {
349 printf("pinctrl: resource \"ppsin\" not found\n");
350 return ret;
351 }
352 priv->mux_in = ioremap(res.start, fdt_resource_size(&res));
353
354 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
355 "ppsout", &res);
356 if (ret < 0) {
357 printf("pinctrl: resource \"ppsout\" not found\n");
358 return ret;
359 }
360 priv->mux_out = ioremap(res.start, fdt_resource_size(&res));
361
362 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
363 "port", &res);
364 if (ret < 0) {
365 printf("pinctrl: resource \"port\" not found\n");
366 return ret;
367 }
368 priv->pinconf = ioremap(res.start, fdt_resource_size(&res));
369
370 return 0;
371 }
372
373 static const struct udevice_id pic32_pinctrl_ids[] = {
374 { .compatible = "microchip,pic32mzda-pinctrl" },
375 { }
376 };
377
378 U_BOOT_DRIVER(pinctrl_pic32) = {
379 .name = "pinctrl_pic32",
380 .id = UCLASS_PINCTRL,
381 .of_match = pic32_pinctrl_ids,
382 .ops = &pic32_pinctrl_ops,
383 .probe = pic32_pinctrl_probe,
384 .bind = dm_scan_fdt_dev,
385 .priv_auto = sizeof(struct pic32_pinctrl_priv),
386 };
387