1 /* 2 * SuperH Pin Function Controller Support 3 * 4 * Copyright (c) 2008 Magnus Damm 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 11 #ifndef __SH_PFC_H 12 #define __SH_PFC_H 13 14 #include <linux/stringify.h> 15 16 enum { 17 PINMUX_TYPE_NONE, 18 PINMUX_TYPE_FUNCTION, 19 PINMUX_TYPE_GPIO, 20 PINMUX_TYPE_OUTPUT, 21 PINMUX_TYPE_INPUT, 22 }; 23 24 #define SH_PFC_PIN_CFG_INPUT (1 << 0) 25 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) 26 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) 27 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) 28 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) 29 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5) 30 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) 31 32 struct sh_pfc_pin { 33 u16 pin; 34 u16 enum_id; 35 const char *name; 36 unsigned int configs; 37 }; 38 39 #define SH_PFC_PIN_GROUP_ALIAS(alias, n) \ 40 { \ 41 .name = #alias, \ 42 .pins = n##_pins, \ 43 .mux = n##_mux, \ 44 .nr_pins = ARRAY_SIZE(n##_pins) + \ 45 BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \ 46 } 47 #define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n) 48 49 struct sh_pfc_pin_group { 50 const char *name; 51 const unsigned int *pins; 52 const unsigned int *mux; 53 unsigned int nr_pins; 54 }; 55 56 /* 57 * Using union vin_data{,12,16} saves memory occupied by the VIN data pins. 58 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups 59 * in this case. It accepts an optional 'version' argument used when the 60 * same group can appear on a different set of pins. 61 */ 62 #define VIN_DATA_PIN_GROUP(n, s, ...) \ 63 { \ 64 .name = #n#s#__VA_ARGS__, \ 65 .pins = n##__VA_ARGS__##_pins.data##s, \ 66 .mux = n##__VA_ARGS__##_mux.data##s, \ 67 .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \ 68 } 69 70 union vin_data12 { 71 unsigned int data12[12]; 72 unsigned int data10[10]; 73 unsigned int data8[8]; 74 }; 75 76 union vin_data16 { 77 unsigned int data16[16]; 78 unsigned int data12[12]; 79 unsigned int data10[10]; 80 unsigned int data8[8]; 81 }; 82 83 union vin_data { 84 unsigned int data24[24]; 85 unsigned int data20[20]; 86 unsigned int data16[16]; 87 unsigned int data12[12]; 88 unsigned int data10[10]; 89 unsigned int data8[8]; 90 unsigned int data4[4]; 91 }; 92 93 #define SH_PFC_FUNCTION(n) \ 94 { \ 95 .name = #n, \ 96 .groups = n##_groups, \ 97 .nr_groups = ARRAY_SIZE(n##_groups), \ 98 } 99 100 struct sh_pfc_function { 101 const char *name; 102 const char * const *groups; 103 unsigned int nr_groups; 104 }; 105 106 struct pinmux_func { 107 u16 enum_id; 108 const char *name; 109 }; 110 111 struct pinmux_cfg_reg { 112 u32 reg; 113 u8 reg_width, field_width; 114 #ifdef DEBUG 115 u16 nr_enum_ids; /* for variable width regs only */ 116 #define SET_NR_ENUM_IDS(n) .nr_enum_ids = n, 117 #else 118 #define SET_NR_ENUM_IDS(n) 119 #endif 120 const u16 *enum_ids; 121 const u8 *var_field_width; 122 }; 123 124 #define GROUP(...) __VA_ARGS__ 125 126 /* 127 * Describe a config register consisting of several fields of the same width 128 * - name: Register name (unused, for documentation purposes only) 129 * - r: Physical register address 130 * - r_width: Width of the register (in bits) 131 * - f_width: Width of the fixed-width register fields (in bits) 132 * - ids: For each register field (from left to right, i.e. MSB to LSB), 133 * 2^f_width enum IDs must be specified, one for each possible 134 * combination of the register field bit values, all wrapped using 135 * the GROUP() macro. 136 */ 137 #define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \ 138 .reg = r, .reg_width = r_width, \ 139 .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \ 140 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ 141 (r_width / f_width) * (1 << f_width)), \ 142 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \ 143 { ids } 144 145 /* 146 * Describe a config register consisting of several fields of different widths 147 * - name: Register name (unused, for documentation purposes only) 148 * - r: Physical register address 149 * - r_width: Width of the register (in bits) 150 * - f_widths: List of widths of the register fields (in bits), from left 151 * to right (i.e. MSB to LSB), wrapped using the GROUP() macro. 152 * - ids: For each register field (from left to right, i.e. MSB to LSB), 153 * 2^f_widths[i] enum IDs must be specified, one for each possible 154 * combination of the register field bit values, all wrapped using 155 * the GROUP() macro. 156 */ 157 #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ 158 .reg = r, .reg_width = r_width, \ 159 .var_field_width = (const u8 []) { f_widths, 0 }, \ 160 SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \ 161 .enum_ids = (const u16 []) { ids } 162 163 struct pinmux_drive_reg_field { 164 u16 pin; 165 u8 offset; 166 u8 size; 167 }; 168 169 struct pinmux_drive_reg { 170 u32 reg; 171 const struct pinmux_drive_reg_field fields[8]; 172 }; 173 174 #define PINMUX_DRIVE_REG(name, r) \ 175 .reg = r, \ 176 .fields = 177 178 struct pinmux_bias_reg { 179 u32 puen; /* Pull-enable or pull-up control register */ 180 u32 pud; /* Pull-up/down control register (optional) */ 181 const u16 pins[32]; 182 }; 183 184 #define PINMUX_BIAS_REG(name1, r1, name2, r2) \ 185 .puen = r1, \ 186 .pud = r2, \ 187 .pins = 188 189 struct pinmux_ioctrl_reg { 190 u32 reg; 191 }; 192 193 struct pinmux_data_reg { 194 u32 reg; 195 u8 reg_width; 196 const u16 *enum_ids; 197 }; 198 199 /* 200 * Describe a data register 201 * - name: Register name (unused, for documentation purposes only) 202 * - r: Physical register address 203 * - r_width: Width of the register (in bits) 204 * - ids: For each register bit (from left to right, i.e. MSB to LSB), one 205 * enum ID must be specified, all wrapped using the GROUP() macro. 206 */ 207 #define PINMUX_DATA_REG(name, r, r_width, ids) \ 208 .reg = r, .reg_width = r_width + \ 209 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ 210 r_width), \ 211 .enum_ids = (const u16 [r_width]) { ids } 212 213 struct pinmux_irq { 214 const short *gpios; 215 }; 216 217 /* 218 * Describe the mapping from GPIOs to a single IRQ 219 * - ids...: List of GPIOs that are mapped to the same IRQ 220 */ 221 #define PINMUX_IRQ(ids...) \ 222 { .gpios = (const short []) { ids, -1 } } 223 224 struct pinmux_range { 225 u16 begin; 226 u16 end; 227 u16 force; 228 }; 229 230 struct sh_pfc_window { 231 phys_addr_t phys; 232 void __iomem *virt; 233 unsigned long size; 234 }; 235 236 struct sh_pfc_pin_range; 237 238 struct sh_pfc { 239 struct device *dev; 240 const struct sh_pfc_soc_info *info; 241 242 void *regs; 243 244 struct sh_pfc_pin_range *ranges; 245 unsigned int nr_ranges; 246 247 unsigned int nr_gpio_pins; 248 249 struct sh_pfc_chip *gpio; 250 }; 251 252 struct sh_pfc_soc_operations { 253 int (*init)(struct sh_pfc *pfc); 254 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); 255 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, 256 unsigned int bias); 257 int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl); 258 }; 259 260 struct sh_pfc_soc_info { 261 const char *name; 262 const struct sh_pfc_soc_operations *ops; 263 264 struct pinmux_range input; 265 struct pinmux_range output; 266 struct pinmux_range function; 267 268 const struct sh_pfc_pin *pins; 269 unsigned int nr_pins; 270 const struct sh_pfc_pin_group *groups; 271 unsigned int nr_groups; 272 const struct sh_pfc_function *functions; 273 unsigned int nr_functions; 274 275 const struct pinmux_cfg_reg *cfg_regs; 276 const struct pinmux_drive_reg *drive_regs; 277 const struct pinmux_bias_reg *bias_regs; 278 const struct pinmux_ioctrl_reg *ioctrl_regs; 279 const struct pinmux_data_reg *data_regs; 280 281 const u16 *pinmux_data; 282 unsigned int pinmux_data_size; 283 284 const struct pinmux_irq *gpio_irq; 285 unsigned int gpio_irq_size; 286 287 u32 unlock_reg; 288 }; 289 290 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg); 291 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data); 292 const struct pinmux_bias_reg * 293 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, 294 unsigned int *bit); 295 296 extern const struct sh_pfc_soc_info r8a774a1_pinmux_info; 297 extern const struct sh_pfc_soc_info r8a774b1_pinmux_info; 298 extern const struct sh_pfc_soc_info r8a774e1_pinmux_info; 299 extern const struct sh_pfc_soc_info r8a7790_pinmux_info; 300 extern const struct sh_pfc_soc_info r8a7791_pinmux_info; 301 extern const struct sh_pfc_soc_info r8a7792_pinmux_info; 302 extern const struct sh_pfc_soc_info r8a7793_pinmux_info; 303 extern const struct sh_pfc_soc_info r8a7794_pinmux_info; 304 extern const struct sh_pfc_soc_info r8a7795_pinmux_info; 305 extern const struct sh_pfc_soc_info r8a7796_pinmux_info; 306 extern const struct sh_pfc_soc_info r8a77965_pinmux_info; 307 extern const struct sh_pfc_soc_info r8a77970_pinmux_info; 308 extern const struct sh_pfc_soc_info r8a77980_pinmux_info; 309 extern const struct sh_pfc_soc_info r8a77990_pinmux_info; 310 extern const struct sh_pfc_soc_info r8a77995_pinmux_info; 311 312 /* ----------------------------------------------------------------------------- 313 * Helper macros to create pin and port lists 314 */ 315 316 /* 317 * sh_pfc_soc_info pinmux_data array macros 318 */ 319 320 /* 321 * Describe generic pinmux data 322 * - data_or_mark: *_DATA or *_MARK enum ID 323 * - ids...: List of enum IDs to associate with data_or_mark 324 */ 325 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 326 327 /* 328 * Describe a pinmux configuration without GPIO function that needs 329 * configuration in a Peripheral Function Select Register (IPSR) 330 * - ipsr: IPSR field (unused, for documentation purposes only) 331 * - fn: Function name, referring to a field in the IPSR 332 */ 333 #define PINMUX_IPSR_NOGP(ipsr, fn) \ 334 PINMUX_DATA(fn##_MARK, FN_##fn) 335 336 /* 337 * Describe a pinmux configuration with GPIO function that needs configuration 338 * in both a Peripheral Function Select Register (IPSR) and in a 339 * GPIO/Peripheral Function Select Register (GPSR) 340 * - ipsr: IPSR field 341 * - fn: Function name, also referring to the IPSR field 342 */ 343 #define PINMUX_IPSR_GPSR(ipsr, fn) \ 344 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) 345 346 /* 347 * Describe a pinmux configuration without GPIO function that needs 348 * configuration in a Peripheral Function Select Register (IPSR), and where the 349 * pinmux function has a representation in a Module Select Register (MOD_SEL). 350 * - ipsr: IPSR field (unused, for documentation purposes only) 351 * - fn: Function name, also referring to the IPSR field 352 * - msel: Module selector 353 */ 354 #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \ 355 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel) 356 357 /* 358 * Describe a pinmux configuration with GPIO function where the pinmux function 359 * has no representation in a Peripheral Function Select Register (IPSR), but 360 * instead solely depends on a group selection. 361 * - gpsr: GPSR field 362 * - fn: Function name, also referring to the GPSR field 363 * - gsel: Group selector 364 */ 365 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \ 366 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel) 367 368 /* 369 * Describe a pinmux configuration with GPIO function that needs configuration 370 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral 371 * Function Select Register (GPSR), and where the pinmux function has a 372 * representation in a Module Select Register (MOD_SEL). 373 * - ipsr: IPSR field 374 * - fn: Function name, also referring to the IPSR field 375 * - msel: Module selector 376 */ 377 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \ 378 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr) 379 380 /* 381 * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with 382 * an additional select register that controls physical multiplexing 383 * with another pin. 384 * - ipsr: IPSR field 385 * - fn: Function name, also referring to the IPSR field 386 * - psel: Physical multiplexing selector 387 * - msel: Module selector 388 */ 389 #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \ 390 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr) 391 392 /* 393 * Describe a pinmux configuration in which a pin is physically multiplexed 394 * with other pins. 395 * - ipsr: IPSR field (unused, for documentation purposes only) 396 * - fn: Function name 397 * - psel: Physical multiplexing selector 398 */ 399 #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \ 400 PINMUX_DATA(fn##_MARK, FN_##psel) 401 402 /* 403 * Describe a pinmux configuration for a single-function pin with GPIO 404 * capability. 405 * - fn: Function name 406 */ 407 #define PINMUX_SINGLE(fn) \ 408 PINMUX_DATA(fn##_MARK, FN_##fn) 409 410 /* 411 * GP port style (32 ports banks) 412 */ 413 414 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ 415 fn(bank, pin, GP_##bank##_##pin, sfx, cfg) 416 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) 417 418 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ 419 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \ 420 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \ 421 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \ 422 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) 423 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) 424 425 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ 426 PORT_GP_CFG_4(bank, fn, sfx, cfg), \ 427 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ 428 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg) 429 #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0) 430 431 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ 432 PORT_GP_CFG_6(bank, fn, sfx, cfg), \ 433 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \ 434 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) 435 #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) 436 437 #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \ 438 PORT_GP_CFG_8(bank, fn, sfx, cfg), \ 439 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg) 440 #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0) 441 442 #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \ 443 PORT_GP_CFG_9(bank, fn, sfx, cfg), \ 444 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg) 445 #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0) 446 447 #define PORT_GP_CFG_11(bank, fn, sfx, cfg) \ 448 PORT_GP_CFG_10(bank, fn, sfx, cfg), \ 449 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg) 450 #define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0) 451 452 #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ 453 PORT_GP_CFG_11(bank, fn, sfx, cfg), \ 454 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) 455 #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) 456 457 #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ 458 PORT_GP_CFG_12(bank, fn, sfx, cfg), \ 459 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \ 460 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg) 461 #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0) 462 463 #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \ 464 PORT_GP_CFG_14(bank, fn, sfx, cfg), \ 465 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg) 466 #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0) 467 468 #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \ 469 PORT_GP_CFG_15(bank, fn, sfx, cfg), \ 470 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg) 471 #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0) 472 473 #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \ 474 PORT_GP_CFG_16(bank, fn, sfx, cfg), \ 475 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg) 476 #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0) 477 478 #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ 479 PORT_GP_CFG_17(bank, fn, sfx, cfg), \ 480 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) 481 #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) 482 483 #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ 484 PORT_GP_CFG_18(bank, fn, sfx, cfg), \ 485 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ 486 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg) 487 #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0) 488 489 #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \ 490 PORT_GP_CFG_20(bank, fn, sfx, cfg), \ 491 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg) 492 #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0) 493 494 #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \ 495 PORT_GP_CFG_21(bank, fn, sfx, cfg), \ 496 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg) 497 #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0) 498 499 #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ 500 PORT_GP_CFG_22(bank, fn, sfx, cfg), \ 501 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) 502 #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) 503 504 #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \ 505 PORT_GP_CFG_23(bank, fn, sfx, cfg), \ 506 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg) 507 #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0) 508 509 #define PORT_GP_CFG_25(bank, fn, sfx, cfg) \ 510 PORT_GP_CFG_24(bank, fn, sfx, cfg), \ 511 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg) 512 #define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0) 513 514 #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ 515 PORT_GP_CFG_25(bank, fn, sfx, cfg), \ 516 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) 517 #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) 518 519 #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ 520 PORT_GP_CFG_26(bank, fn, sfx, cfg), \ 521 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \ 522 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) 523 #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0) 524 525 #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \ 526 PORT_GP_CFG_28(bank, fn, sfx, cfg), \ 527 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg) 528 #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0) 529 530 #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ 531 PORT_GP_CFG_29(bank, fn, sfx, cfg), \ 532 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) 533 #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0) 534 535 #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ 536 PORT_GP_CFG_30(bank, fn, sfx, cfg), \ 537 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \ 538 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) 539 #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0) 540 541 #define PORT_GP_32_REV(bank, fn, sfx) \ 542 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ 543 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ 544 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ 545 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ 546 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ 547 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ 548 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ 549 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ 550 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ 551 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ 552 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ 553 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ 554 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ 555 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ 556 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ 557 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) 558 559 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ 560 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx 561 #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) 562 563 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ 564 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ 565 { \ 566 .pin = (bank * 32) + _pin, \ 567 .name = __stringify(_name), \ 568 .enum_id = _name##_DATA, \ 569 .configs = cfg, \ 570 } 571 #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) 572 573 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ 574 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) 575 #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) 576 577 /* 578 * PORT style (linear pin space) 579 */ 580 581 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx) 582 583 #define PORT_10(pn, fn, pfx, sfx) \ 584 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \ 585 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \ 586 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \ 587 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \ 588 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx) 589 590 #define PORT_90(pn, fn, pfx, sfx) \ 591 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \ 592 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \ 593 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \ 594 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \ 595 PORT_10(pn+90, fn, pfx##9, sfx) 596 597 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ 598 #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx 599 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) 600 601 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ 602 #define PINMUX_GPIO(_pin) \ 603 [GPIO_##_pin] = { \ 604 .pin = (u16)-1, \ 605 .name = __stringify(GPIO_##_pin), \ 606 .enum_id = _pin##_DATA, \ 607 } 608 609 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ 610 #define SH_PFC_PIN_CFG(_pin, cfgs) \ 611 { \ 612 .pin = _pin, \ 613 .name = __stringify(PORT##_pin), \ 614 .enum_id = PORT##_pin##_DATA, \ 615 .configs = cfgs, \ 616 } 617 618 /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */ 619 #define SH_PFC_PIN_NAMED(row, col, _name) \ 620 { \ 621 .pin = PIN_NUMBER(row, col), \ 622 .name = __stringify(PIN_##_name), \ 623 .configs = SH_PFC_PIN_CFG_NO_GPIO, \ 624 } 625 626 /* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */ 627 #define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \ 628 { \ 629 .pin = PIN_NUMBER(row, col), \ 630 .name = __stringify(PIN_##_name), \ 631 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \ 632 } 633 634 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, 635 * PORT_name_OUT, PORT_name_IN marks 636 */ 637 #define _PORT_DATA(pn, pfx, sfx) \ 638 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \ 639 PORT##pfx##_OUT, PORT##pfx##_IN) 640 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) 641 642 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ 643 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ 644 [gpio - (base)] = { \ 645 .name = __stringify(gpio), \ 646 .enum_id = data_or_mark, \ 647 } 648 #define GPIO_FN(str) \ 649 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) 650 651 /* 652 * PORTnCR helper macro for SH-Mobile/R-Mobile 653 */ 654 #define PORTCR(nr, reg) \ 655 { \ 656 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \ 657 GROUP(2, 2, 1, 3), \ 658 GROUP( \ 659 /* PULMD[1:0], handled by .set_bias() */ \ 660 0, 0, 0, 0, \ 661 /* IE and OE */ \ 662 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ 663 /* SEC, not supported */ \ 664 0, 0, \ 665 /* PTMD[2:0] */ \ 666 PORT##nr##_FN0, PORT##nr##_FN1, \ 667 PORT##nr##_FN2, PORT##nr##_FN3, \ 668 PORT##nr##_FN4, PORT##nr##_FN5, \ 669 PORT##nr##_FN6, PORT##nr##_FN7 \ 670 )) \ 671 } 672 673 /* 674 * GPIO number helper macro for R-Car 675 */ 676 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) 677 678 #include <linux/bug.h> 679 #endif /* __SH_PFC_H */ 680