1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
5 *
6 * Based on Rockchip's drivers/power/pmic/pmic_act8846.c:
7 * Copyright (C) 2012 rockchips
8 * zyw <zyw@rock-chips.com>
9 */
10
11 #include <common.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <power/act8846_pmic.h>
15 #include <power/pmic.h>
16 #include <power/regulator.h>
17
18 static const u16 voltage_map[] = {
19 600, 625, 650, 675, 700, 725, 750, 775,
20 800, 825, 850, 875, 900, 925, 950, 975,
21 1000, 1025, 1050, 1075, 1100, 1125, 1150, 1175,
22 1200, 1250, 1300, 1350, 1400, 1450, 1500, 1550,
23 1600, 1650, 1700, 1750, 1800, 1850, 1900, 1950,
24 2000, 2050, 2100, 2150, 2200, 2250, 2300, 2350,
25 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100,
26 3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900,
27 };
28
29 enum {
30 REG_SYS0,
31 REG_SYS1,
32 REG1_VOL = 0x10,
33 REG1_CTL = 0X11,
34 REG2_VOL0 = 0x20,
35 REG2_VOL1,
36 REG2_CTL,
37 REG3_VOL0 = 0x30,
38 REG3_VOL1,
39 REG3_CTL,
40 REG4_VOL0 = 0x40,
41 REG4_VOL1,
42 REG4_CTL,
43 REG5_VOL = 0x50,
44 REG5_CTL,
45 REG6_VOL = 0X58,
46 REG6_CTL,
47 REG7_VOL = 0x60,
48 REG7_CTL,
49 REG8_VOL = 0x68,
50 REG8_CTL,
51 REG9_VOL = 0x70,
52 REG9_CTL,
53 REG10_VOL = 0x80,
54 REG10_CTL,
55 REG11_VOL = 0x90,
56 REG11_CTL,
57 REG12_VOL = 0xa0,
58 REG12_CTL,
59 REG13 = 0xb1,
60 };
61
62 static const u8 addr_vol[] = {
63 0, REG1_VOL, REG2_VOL0, REG3_VOL0, REG4_VOL0,
64 REG5_VOL, REG6_VOL, REG7_VOL, REG8_VOL, REG9_VOL,
65 REG10_VOL, REG11_VOL, REG12_VOL,
66 };
67
68 static const u8 addr_ctl[] = {
69 0, REG1_CTL, REG2_CTL, REG3_CTL, REG4_CTL,
70 REG5_CTL, REG6_CTL, REG7_CTL, REG8_CTL, REG9_CTL,
71 REG10_CTL, REG11_CTL, REG12_CTL,
72 };
73
check_volt_table(const u16 * volt_table,int uvolt)74 static int check_volt_table(const u16 *volt_table, int uvolt)
75 {
76 int i;
77
78 for (i = VOL_MIN_IDX; i < VOL_MAX_IDX; i++) {
79 if (uvolt <= (volt_table[i] * 1000))
80 return i;
81 }
82 return -EINVAL;
83 }
84
reg_get_value(struct udevice * dev)85 static int reg_get_value(struct udevice *dev)
86 {
87 int reg = dev->driver_data;
88 int ret;
89
90 ret = pmic_reg_read(dev->parent, addr_vol[reg]);
91 if (ret < 0)
92 return ret;
93
94 return voltage_map[ret & LDO_VOL_MASK] * 1000;
95 }
96
reg_set_value(struct udevice * dev,int uvolt)97 static int reg_set_value(struct udevice *dev, int uvolt)
98 {
99 int reg = dev->driver_data;
100 int val;
101
102 val = check_volt_table(voltage_map, uvolt);
103 if (val < 0)
104 return val;
105
106 return pmic_clrsetbits(dev->parent, addr_vol[reg], LDO_VOL_MASK, val);
107 }
108
reg_set_enable(struct udevice * dev,bool enable)109 static int reg_set_enable(struct udevice *dev, bool enable)
110 {
111 int reg = dev->driver_data;
112
113 return pmic_clrsetbits(dev->parent, addr_ctl[reg], LDO_EN_MASK,
114 enable ? LDO_EN_MASK : 0);
115 }
116
reg_get_enable(struct udevice * dev)117 static int reg_get_enable(struct udevice *dev)
118 {
119 int reg = dev->driver_data;
120 int ret;
121
122 ret = pmic_reg_read(dev->parent, addr_ctl[reg]);
123 if (ret < 0)
124 return ret;
125
126 return ret & LDO_EN_MASK ? true : false;
127 }
128
act8846_reg_probe(struct udevice * dev)129 static int act8846_reg_probe(struct udevice *dev)
130 {
131 struct dm_regulator_uclass_plat *uc_pdata;
132 int reg = dev->driver_data;
133
134 uc_pdata = dev_get_uclass_plat(dev);
135
136 uc_pdata->type = reg <= 4 ? REGULATOR_TYPE_BUCK : REGULATOR_TYPE_LDO;
137 uc_pdata->mode_count = 0;
138
139 return 0;
140 }
141
142 static const struct dm_regulator_ops act8846_reg_ops = {
143 .get_value = reg_get_value,
144 .set_value = reg_set_value,
145 .get_enable = reg_get_enable,
146 .set_enable = reg_set_enable,
147 };
148
149 U_BOOT_DRIVER(act8846_buck) = {
150 .name = "act8846_reg",
151 .id = UCLASS_REGULATOR,
152 .ops = &act8846_reg_ops,
153 .probe = act8846_reg_probe,
154 };
155