1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Google Inc.
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <log.h>
9 #include <pwm.h>
10 #include <asm/io.h>
11 #include <asm/arch/clk.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/pwm.h>
14
15 struct exynos_pwm_priv {
16 struct s5p_timer *regs;
17 };
18
exynos_pwm_set_config(struct udevice * dev,uint channel,uint period_ns,uint duty_ns)19 static int exynos_pwm_set_config(struct udevice *dev, uint channel,
20 uint period_ns, uint duty_ns)
21 {
22 struct exynos_pwm_priv *priv = dev_get_priv(dev);
23 struct s5p_timer *regs = priv->regs;
24 unsigned int offset, prescaler;
25 uint div = 4, rate, rate_ns;
26 u32 val;
27 u32 tcnt, tcmp, tcon;
28
29 if (channel >= 5)
30 return -EINVAL;
31 debug("%s: Configure '%s' channel %u, period_ns %u, duty_ns %u\n",
32 __func__, dev->name, channel, period_ns, duty_ns);
33
34 val = readl(®s->tcfg0);
35 prescaler = (channel < 2 ? val : (val >> 8)) & 0xff;
36 div = (readl(®s->tcfg1) >> MUX_DIV_SHIFT(channel)) & 0xf;
37
38 rate = get_pwm_clk() / ((prescaler + 1) * (1 << div));
39 debug("%s: pwm_clk %lu, rate %u\n", __func__, get_pwm_clk(), rate);
40
41 if (channel < 4) {
42 rate_ns = 1000000000 / rate;
43 tcnt = period_ns / rate_ns;
44 tcmp = duty_ns / rate_ns;
45 debug("%s: tcnt %u, tcmp %u\n", __func__, tcnt, tcmp);
46 offset = channel * 3;
47 writel(tcnt, ®s->tcntb0 + offset);
48 writel(tcmp, ®s->tcmpb0 + offset);
49 }
50
51 tcon = readl(®s->tcon);
52 tcon |= TCON_UPDATE(channel);
53 if (channel < 4)
54 tcon |= TCON_AUTO_RELOAD(channel);
55 else
56 tcon |= TCON4_AUTO_RELOAD;
57 writel(tcon, ®s->tcon);
58
59 tcon &= ~TCON_UPDATE(channel);
60 writel(tcon, ®s->tcon);
61
62 return 0;
63 }
64
exynos_pwm_set_enable(struct udevice * dev,uint channel,bool enable)65 static int exynos_pwm_set_enable(struct udevice *dev, uint channel,
66 bool enable)
67 {
68 struct exynos_pwm_priv *priv = dev_get_priv(dev);
69 struct s5p_timer *regs = priv->regs;
70 u32 mask;
71
72 if (channel >= 4)
73 return -EINVAL;
74 debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
75 mask = TCON_START(channel);
76 clrsetbits_le32(®s->tcon, mask, enable ? mask : 0);
77
78 return 0;
79 }
80
exynos_pwm_probe(struct udevice * dev)81 static int exynos_pwm_probe(struct udevice *dev)
82 {
83 struct exynos_pwm_priv *priv = dev_get_priv(dev);
84 struct s5p_timer *regs = priv->regs;
85
86 writel(PRESCALER_0 | PRESCALER_1 << 8, ®s->tcfg0);
87
88 return 0;
89 }
90
exynos_pwm_of_to_plat(struct udevice * dev)91 static int exynos_pwm_of_to_plat(struct udevice *dev)
92 {
93 struct exynos_pwm_priv *priv = dev_get_priv(dev);
94
95 priv->regs = dev_read_addr_ptr(dev);
96
97 return 0;
98 }
99
100 static const struct pwm_ops exynos_pwm_ops = {
101 .set_config = exynos_pwm_set_config,
102 .set_enable = exynos_pwm_set_enable,
103 };
104
105 static const struct udevice_id exynos_channels[] = {
106 { .compatible = "samsung,exynos4210-pwm" },
107 { }
108 };
109
110 U_BOOT_DRIVER(exynos_pwm) = {
111 .name = "exynos_pwm",
112 .id = UCLASS_PWM,
113 .of_match = exynos_channels,
114 .ops = &exynos_pwm_ops,
115 .probe = exynos_pwm_probe,
116 .of_to_plat = exynos_pwm_of_to_plat,
117 .priv_auto = sizeof(struct exynos_pwm_priv),
118 };
119