1if RAM || SPL_RAM
2
3config ASPEED_DDR4_DUALX8
4	bool "Enable Dual X8 DDR4 die"
5	depends on DM && OF_CONTROL && ARCH_ASPEED
6	default n
7	help
8		Say Y if dual X8 DDR4 die is used on the board.  The aspeed ddr sdram
9		controller needs to know if the memory chip mounted on the board is dual
10		 x8 die or not.  Or it may get the wrong size of the memory space.
11
12if ASPEED_AST2600
13
14choice
15	prompt "DDR4 target date rate"
16	default ASPEED_DDR4_1600
17
18config ASPEED_DDR4_400
19	bool "DDR4 targets at 400Mbps"
20	depends on DM && OF_CONTROL && ARCH_ASPEED
21	help
22	  select DDR4 target data rate at 400M
23
24config ASPEED_DDR4_800
25	bool "DDR4 targets at 800Mbps"
26	depends on DM && OF_CONTROL && ARCH_ASPEED
27	help
28	  select DDR4 target data rate at 800M
29
30config ASPEED_DDR4_1333
31	bool "DDR4 targets at 1333Mbps"
32	depends on DM && OF_CONTROL && ARCH_ASPEED
33	help
34	  select DDR4 target data rate at 1333M
35
36config ASPEED_DDR4_1600
37	bool "DDR4 targets at 1600Mbps"
38	depends on DM && OF_CONTROL && ARCH_ASPEED
39	help
40	  select DDR4 target data rate at 1600M
41endchoice
42
43config ASPEED_BYPASS_SELFTEST
44	bool "bypass self test during DRAM initialization"
45	default n
46	help
47	  Say Y here to bypass DRAM self test to speed up the boot time
48
49config ASPEED_ECC
50	bool "aspeed SDRAM error correcting code"
51	depends on DM && OF_CONTROL && ARCH_ASPEED
52	default n
53	help
54	  enable SDRAM ECC function
55
56if ASPEED_ECC
57config ASPEED_ECC_SIZE
58	int "ECC size: 0=driver auto-caluated"
59	depends on ASPEED_ECC
60	default 0
61	help
62	  SDRAM size with the error correcting code enabled. The unit is
63	  in Megabytes.  Noted that only the 8/9 of the configured size
64	  can be used by the system.  The remaining 1/9 will be used by
65	  the ECC engine.  If the size is set to 0, the sdram driver will
66	  calculate the SDRAM size and set the whole range be ECC enabled.
67endif # end of ASPEED_ECC
68endif # end of ASPEED_AST2600
69endif # end of RAM || SPL_RAM
70