1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /********************************************************************** 3 * Copyright (C) 2012-2019 Cadence Design Systems, Inc. 4 ********************************************************************** 5 * WARNING: This file is auto-generated using api-generator utility. 6 * api-generator: 12.02.13bb8d5 7 * Do not edit it manually. 8 ********************************************************************** 9 * Cadence Core Driver for LPDDR4. 10 ********************************************************************** 11 */ 12 13 #ifndef LPDDR4_IF_H 14 #define LPDDR4_IF_H 15 16 #include <linux/types.h> 17 18 /** @defgroup ConfigInfo Configuration and Hardware Operation Information 19 * The following definitions specify the driver operation environment that 20 * is defined by hardware configuration or client code. These defines are 21 * located in the header file of the core driver. 22 * @{ 23 */ 24 25 /********************************************************************** 26 * Defines 27 **********************************************************************/ 28 /** Number of chip-selects */ 29 #define LPDDR4_MAX_CS (2U) 30 31 /** Number of accessible registers for controller. */ 32 #define LPDDR4_CTL_REG_COUNT (459U) 33 34 /** Number of accessible registers for PHY Independent Module. */ 35 #define LPDDR4_PHY_INDEP_REG_COUNT (300U) 36 37 /** Number of accessible registers for PHY. */ 38 #define LPDDR4_PHY_REG_COUNT (1423U) 39 40 /** 41 * @} 42 */ 43 44 /** @defgroup DataStructure Dynamic Data Structures 45 * This section defines the data structures used by the driver to provide 46 * hardware information, modification and dynamic operation of the driver. 47 * These data structures are defined in the header file of the core driver 48 * and utilized by the API. 49 * @{ 50 */ 51 52 /********************************************************************** 53 * Forward declarations 54 **********************************************************************/ 55 typedef struct lpddr4_config_s lpddr4_config; 56 typedef struct lpddr4_privatedata_s lpddr4_privatedata; 57 typedef struct lpddr4_debuginfo_s lpddr4_debuginfo; 58 typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs; 59 typedef struct lpddr4_reginitdata_s lpddr4_reginitdata; 60 61 /********************************************************************** 62 * Enumerations 63 **********************************************************************/ 64 /** This is used to indicate whether the Controller, PHY, or PHY Independent module is addressed. */ 65 typedef enum 66 { 67 LPDDR4_CTL_REGS = 0U, 68 LPDDR4_PHY_REGS = 1U, 69 LPDDR4_PHY_INDEP_REGS = 2U 70 } lpddr4_regblock; 71 72 /** Controller status or error interrupts. */ 73 typedef enum 74 { 75 LPDDR4_RESET_DONE = 0U, 76 LPDDR4_BUS_ACCESS_ERROR = 1U, 77 LPDDR4_MULTIPLE_BUS_ACCESS_ERROR = 2U, 78 LPDDR4_ECC_MULTIPLE_CORR_ERROR = 3U, 79 LPDDR4_ECC_MULTIPLE_UNCORR_ERROR = 4U, 80 LPDDR4_ECC_WRITEBACK_EXEC_ERROR = 5U, 81 LPDDR4_ECC_SCRUB_DONE = 6U, 82 LPDDR4_ECC_SCRUB_ERROR = 7U, 83 LPDDR4_PORT_COMMAND_ERROR = 8U, 84 LPDDR4_MC_INIT_DONE = 9U, 85 LPDDR4_LP_DONE = 10U, 86 LPDDR4_BIST_DONE = 11U, 87 LPDDR4_WRAP_ERROR = 12U, 88 LPDDR4_INVALID_BURST_ERROR = 13U, 89 LPDDR4_RDLVL_ERROR = 14U, 90 LPDDR4_RDLVL_GATE_ERROR = 15U, 91 LPDDR4_WRLVL_ERROR = 16U, 92 LPDDR4_CA_TRAINING_ERROR = 17U, 93 LPDDR4_DFI_UPDATE_ERROR = 18U, 94 LPDDR4_MRR_ERROR = 19U, 95 LPDDR4_PHY_MASTER_ERROR = 20U, 96 LPDDR4_WRLVL_REQ = 21U, 97 LPDDR4_RDLVL_REQ = 22U, 98 LPDDR4_RDLVL_GATE_REQ = 23U, 99 LPDDR4_CA_TRAINING_REQ = 24U, 100 LPDDR4_LEVELING_DONE = 25U, 101 LPDDR4_PHY_ERROR = 26U, 102 LPDDR4_MR_READ_DONE = 27U, 103 LPDDR4_TEMP_CHANGE = 28U, 104 LPDDR4_TEMP_ALERT = 29U, 105 LPDDR4_SW_DQS_COMPLETE = 30U, 106 LPDDR4_DQS_OSC_BV_UPDATED = 31U, 107 LPDDR4_DQS_OSC_OVERFLOW = 32U, 108 LPDDR4_DQS_OSC_VAR_OUT = 33U, 109 LPDDR4_MR_WRITE_DONE = 34U, 110 LPDDR4_INHIBIT_DRAM_DONE = 35U, 111 LPDDR4_DFI_INIT_STATE = 36U, 112 LPDDR4_DLL_RESYNC_DONE = 37U, 113 LPDDR4_TDFI_TO = 38U, 114 LPDDR4_DFS_DONE = 39U, 115 LPDDR4_DFS_STATUS = 40U, 116 LPDDR4_REFRESH_STATUS = 41U, 117 LPDDR4_ZQ_STATUS = 42U, 118 LPDDR4_SW_REQ_MODE = 43U, 119 LPDDR4_LOR_BITS = 44U 120 } lpddr4_ctlinterrupt; 121 122 /** PHY Independent Module status or error interrupts. */ 123 typedef enum 124 { 125 LPDDR4_PHY_INDEP_INIT_DONE_BIT = 0U, 126 LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT = 1U, 127 LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT = 2U, 128 LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT = 3U, 129 LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT = 4U, 130 LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT = 5U, 131 LPDDR4_PHY_INDEP_CALVL_ERROR_BIT = 6U, 132 LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT = 7U, 133 LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT = 8U, 134 LPDDR4_PHY_INDEP_RDLVL_REQ_BIT = 9U, 135 LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U, 136 LPDDR4_PHY_INDEP_WRLVL_REQ_BIT = 11U, 137 LPDDR4_PHY_INDEP_CALVL_REQ_BIT = 12U, 138 LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT = 13U, 139 LPDDR4_PHY_INDEP_LVL_DONE_BIT = 14U, 140 LPDDR4_PHY_INDEP_BIST_DONE_BIT = 15U, 141 LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U, 142 LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U 143 } lpddr4_phyindepinterrupt; 144 145 /** List of informations and warnings from driver. */ 146 typedef enum 147 { 148 LPDDR4_DRV_NONE = 0U, 149 LPDDR4_DRV_SOC_PLL_UPDATE = 1U 150 } lpddr4_infotype; 151 152 /** Low power interface wake up timing parameters */ 153 typedef enum 154 { 155 LPDDR4_LPI_PD_WAKEUP_FN = 0U, 156 LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U, 157 LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U, 158 LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U, 159 LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U, 160 LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U, 161 LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U 162 } lpddr4_lpiwakeupparam; 163 164 /** Half Datapath mode setting */ 165 typedef enum 166 { 167 LPDDR4_REDUC_ON = 0U, 168 LPDDR4_REDUC_OFF = 1U 169 } lpddr4_reducmode; 170 171 /** ECC Control parameter setting */ 172 typedef enum 173 { 174 LPDDR4_ECC_DISABLED = 0U, 175 LPDDR4_ECC_ENABLED = 1U, 176 LPDDR4_ECC_ERR_DETECT = 2U, 177 LPDDR4_ECC_ERR_DETECT_CORRECT = 3U 178 } lpddr4_eccenable; 179 180 /** Data Byte Inversion mode setting */ 181 typedef enum 182 { 183 LPDDR4_DBI_RD_ON = 0U, 184 LPDDR4_DBI_RD_OFF = 1U, 185 LPDDR4_DBI_WR_ON = 2U, 186 LPDDR4_DBI_WR_OFF = 3U 187 } lpddr4_dbimode; 188 189 /** Controller Frequency Set Point number */ 190 typedef enum 191 { 192 LPDDR4_FSP_0 = 0U, 193 LPDDR4_FSP_1 = 1U, 194 LPDDR4_FSP_2 = 2U 195 } lpddr4_ctlfspnum; 196 197 /********************************************************************** 198 * Callbacks 199 **********************************************************************/ 200 /** 201 * Reports informations and warnings that need to be communicated. 202 * Params: 203 * pD - driver state info specific to this instance. 204 * infoType - Type of information. 205 */ 206 typedef void (*lpddr4_infocallback)(const lpddr4_privatedata* pd, lpddr4_infotype infotype); 207 208 /** 209 * Reports interrupts received by the controller. 210 * Params: 211 * pD - driver state info specific to this instance. 212 * ctlInterrupt - Interrupt raised 213 * chipSelect - Chip for which interrupt raised 214 */ 215 typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt ctlinterrupt, uint8_t chipselect); 216 217 /** 218 * Reports interrupts received by the PHY Independent Module. 219 * Params: 220 * privateData - driver state info specific to this instance. 221 * phyIndepInterrupt - Interrupt raised 222 * chipSelect - Chip for which interrupt raised 223 */ 224 typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt phyindepinterrupt, uint8_t chipselect); 225 226 /** 227 * @} 228 */ 229 230 /** @defgroup DriverFunctionAPI Driver Function API 231 * Prototypes for the driver API functions. The user application can link statically to the 232 * necessary API functions and call them directly. 233 * @{ 234 */ 235 236 /********************************************************************** 237 * API methods 238 **********************************************************************/ 239 240 /** 241 * Checks configuration object. 242 * @param[in] config Driver/hardware configuration required. 243 * @param[out] configSize Size of memory allocations required. 244 * @return CDN_EOK on success (requirements structure filled). 245 * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints. 246 */ 247 uint32_t lpddr4_probe(const lpddr4_config* config, uint16_t* configsize); 248 249 /** 250 * Init function to be called after LPDDR4_probe() to set up the 251 * driver configuration. Memory should be allocated for drv_data 252 * (using the size determined using LPDDR4_probe) before calling this 253 * API. init_settings should be initialised with base addresses for 254 * PHY Indepenent Module, Controller and PHY before calling this 255 * function. If callbacks are required for interrupt handling, these 256 * should also be configured in init_settings. 257 * @param[in] pD Driver state info specific to this instance. 258 * @param[in] cfg Specifies driver/hardware configuration. 259 * @return CDN_EOK on success 260 * @return EINVAL if illegal/inconsistent values in cfg. 261 * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters. 262 */ 263 uint32_t lpddr4_init(lpddr4_privatedata* pd, const lpddr4_config* cfg); 264 265 /** 266 * Start the driver. 267 * @param[in] pD Driver state info specific to this instance. 268 */ 269 uint32_t lpddr4_start(const lpddr4_privatedata* pd); 270 271 /** 272 * Read a register from the controller, PHY or PHY Independent Module 273 * @param[in] pD Driver state info specific to this instance. 274 * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register 275 * @param[in] regOffset Register offset 276 * @param[out] regValue Register value read 277 * @return CDN_EOK on success. 278 * @return EINVAL if regOffset if out of range or regValue is NULL 279 */ 280 uint32_t lpddr4_readreg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue); 281 282 /** 283 * Write a register in the controller, PHY or PHY Independent Module 284 * @param[in] pD Driver state info specific to this instance. 285 * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register 286 * @param[in] regOffset Register offset 287 * @param[in] regValue Register value to be written 288 * @return CDN_EOK on success. 289 * @return EINVAL if regOffset is out of range or regValue is NULL 290 */ 291 uint32_t lpddr4_writereg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue); 292 293 /** 294 * Read a memory mode register from DRAM 295 * @param[in] pD Driver state info specific to this instance. 296 * @param[in] readModeRegVal Value to set in 'read_modereg' parameter. 297 * @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices. 298 * @param[out] mmrStatus Status of mode register read(mrr) instruction. 299 * @return CDN_EOK on success. 300 * @return EINVAL if regNumber is out of range or regValue is NULL 301 */ 302 uint32_t lpddr4_getmmrregister(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus); 303 304 /** 305 * Write a memory mode register in DRAM 306 * @param[in] pD Driver state info specific to this instance. 307 * @param[in] writeModeRegVal Value to set in 'write_modereg' parameter. 308 * @param[out] mrwStatus Status of mode register write(mrw) instruction. 309 * @return CDN_EOK on success. 310 * @return EINVAL if regNumber is out of range or regValue is NULL 311 */ 312 uint32_t lpddr4_setmmrregister(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus); 313 314 /** 315 * Write a set of initialisation values to the controller registers 316 * @param[in] pD Driver state info specific to this instance. 317 * @param[in] regValues Register values to be written 318 * @return CDN_EOK on success. 319 * @return EINVAL if regValues is NULL 320 */ 321 uint32_t lpddr4_writectlconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues); 322 323 /** 324 * Write a set of initialisation values to the PHY registers 325 * @param[in] pD Driver state info specific to this instance. 326 * @param[in] regValues Register values to be written 327 * @return CDN_EOK on success. 328 * @return EINVAL if regValues is NULL 329 */ 330 uint32_t lpddr4_writephyconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues); 331 332 /** 333 * Write a set of initialisation values to the PHY Independent Module 334 * registers 335 * @param[in] pD Driver state info specific to this instance. 336 * @param[in] regValues Register values to be written 337 * @return CDN_EOK on success. 338 * @return EINVAL if regValues is NULL 339 */ 340 uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues); 341 342 /** 343 * Read values of the controller registers in bulk (Set 'updateCtlReg' 344 * to read) and store in memory. 345 * @param[in] pD Driver state info specific to this instance. 346 * @param[out] regValues Register values which are read 347 * @return CDN_EOK on success. 348 * @return EINVAL if regValues is NULL 349 */ 350 uint32_t lpddr4_readctlconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues); 351 352 /** 353 * Read the values of the PHY module registers in bulk (Set 354 * 'updatePhyReg' to read) and store in memory. 355 * @param[in] pD Driver state info specific to this instance. 356 * @param[out] regValues Register values which are read 357 * @return CDN_EOK on success. 358 * @return EINVAL if regValues is NULL 359 */ 360 uint32_t lpddr4_readphyconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues); 361 362 /** 363 * Read the values of the PHY Independent module registers in bulk(Set 364 * 'updatePhyIndepReg' to read) and store in memory. 365 * @param[in] pD Driver state info specific to this instance. 366 * @param[out] regValues Register values which are read 367 * @return CDN_EOK on success. 368 * @return EINVAL if regValues is NULL 369 */ 370 uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues); 371 372 /** 373 * Read the current interrupt mask for the controller 374 * @param[in] pD Driver state info specific to this instance. 375 * @param[out] mask Value of interrupt mask 376 * @return CDN_EOK on success. 377 * @return EINVAL if mask pointer is NULL 378 */ 379 uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata* pd, uint64_t* mask); 380 381 /** 382 * Sets the interrupt mask for the controller 383 * @param[in] pD Driver state info specific to this instance. 384 * @param[in] mask Value of interrupt mask to be written 385 * @return CDN_EOK on success. 386 * @return EINVAL if mask pointer is NULL 387 */ 388 uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata* pd, const uint64_t* mask); 389 390 /** 391 * Check whether a specific controller interrupt is active 392 * @param[in] pD Driver state info specific to this instance. 393 * @param[in] intr Interrupt to be checked 394 * @param[out] irqStatus Status of the interrupt, TRUE if active 395 * @return CDN_EOK on success. 396 * @return EINVAL if intr is not valid 397 */ 398 uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus); 399 400 /** 401 * Acknowledge a specific controller interrupt 402 * @param[in] pD Driver state info specific to this instance. 403 * @param[in] intr Interrupt to be acknowledged 404 * @return CDN_EOK on success. 405 * @return EINVAL if intr is not valid 406 */ 407 uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr); 408 409 /** 410 * Read the current interrupt mask for the PHY Independent Module 411 * @param[in] pD Driver state info specific to this instance. 412 * @param[out] mask Value of interrupt mask 413 * @return CDN_EOK on success. 414 * @return EINVAL if mask pointer is NULL 415 */ 416 uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata* pd, uint32_t* mask); 417 418 /** 419 * Sets the interrupt mask for the PHY Independent Module 420 * @param[in] pD Driver state info specific to this instance. 421 * @param[in] mask Value of interrupt mask to be written 422 * @return CDN_EOK on success. 423 * @return EINVAL if mask pointer is NULL 424 */ 425 uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata* pd, const uint32_t* mask); 426 427 /** 428 * Check whether a specific PHY Independent Module interrupt is active 429 * @param[in] pD Driver state info specific to this instance. 430 * @param[in] intr Interrupt to be checked 431 * @param[out] irqStatus Status of the interrupt, TRUE if active 432 * @return CDN_EOK on success. 433 * @return EINVAL if intr is not valid 434 */ 435 uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus); 436 437 /** 438 * Acknowledge a specific PHY Independent Module interrupt 439 * @param[in] pD Driver state info specific to this instance. 440 * @param[in] intr Interrupt to be acknowledged 441 * @return CDN_EOK on success. 442 * @return EINVAL if intr is not valid 443 */ 444 uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr); 445 446 /** 447 * Retrieve status information after a failed init. The 448 * DebugStructInfo will be filled in with error codes which can be 449 * referenced against the driver documentation for further details. 450 * @param[in] pD Driver state info specific to this instance. 451 * @param[out] debugInfo status 452 * @return CDN_EOK on success. 453 * @return EINVAL if debugInfo is NULL 454 */ 455 uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo); 456 457 /** 458 * Get the current value of Low power Interface wake up time. 459 * @param[in] pD Driver state info specific to this instance. 460 * @param[in] lpiWakeUpParam LPI timing parameter 461 * @param[in] fspNum Frequency copy 462 * @param[out] cycles Timing value(in cycles) 463 * @return CDN_EOK on success. 464 * @return EINVAL if powerMode is NULL 465 */ 466 uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles); 467 468 /** 469 * Set the current value of Low power Interface wake up time. 470 * @param[in] pD Driver state info specific to this instance. 471 * @param[in] lpiWakeUpParam LPI timing parameter 472 * @param[in] fspNum Frequency copy 473 * @param[in] cycles Timing value(in cycles) 474 * @return CDN_EOK on success. 475 * @return EINVAL if powerMode is NULL 476 */ 477 uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles); 478 479 /** 480 * Get the current value for ECC auto correction 481 * @param[in] pD Driver state info specific to this instance. 482 * @param[out] eccParam ECC parameter setting 483 * @return CDN_EOK on success. 484 * @return EINVAL if on_off is NULL 485 */ 486 uint32_t lpddr4_geteccenable(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam); 487 488 /** 489 * Set the value for ECC auto correction. This API must be called 490 * before startup of memory. 491 * @param[in] pD Driver state info specific to this instance. 492 * @param[in] eccParam ECC control parameter setting 493 * @return CDN_EOK on success. 494 * @return EINVAL if on_off is NULL 495 */ 496 uint32_t lpddr4_seteccenable(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam); 497 498 /** 499 * Get the current value for the Half Datapath option 500 * @param[in] pD Driver state info specific to this instance. 501 * @param[out] mode Half Datapath setting 502 * @return CDN_EOK on success. 503 * @return EINVAL if mode is NULL 504 */ 505 uint32_t lpddr4_getreducmode(const lpddr4_privatedata* pd, lpddr4_reducmode* mode); 506 507 /** 508 * Set the value for the Half Datapath option. This API must be 509 * called before startup of memory. 510 * @param[in] pD Driver state info specific to this instance. 511 * @param[in] mode Half Datapath setting 512 * @return CDN_EOK on success. 513 * @return EINVAL if mode is NULL 514 */ 515 uint32_t lpddr4_setreducmode(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode); 516 517 /** 518 * Get the current value for Data Bus Inversion setting. This will be 519 * compared with the current DRAM setting using the MR3 register. 520 * @param[in] pD Driver state info specific to this instance. 521 * @param[out] on_off DBI read value 522 * @return CDN_EOK on success. 523 * @return EINVAL if on_off is NULL 524 */ 525 uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata* pd, bool* on_off); 526 527 /** 528 * Get the current value for Data Bus Inversion setting. This will be 529 * compared with the current DRAM setting using the MR3 register. 530 * @param[in] pD Driver state info specific to this instance. 531 * @param[out] on_off DBI write value 532 * @return CDN_EOK on success. 533 * @return EINVAL if on_off is NULL 534 */ 535 uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata* pd, bool* on_off); 536 537 /** 538 * Set the mode for Data Bus Inversion. This will also be set in DRAM 539 * using the MR3 controller register. This API must be called before 540 * startup of memory. 541 * @param[in] pD Driver state info specific to this instance. 542 * @param[in] mode status 543 * @return CDN_EOK on success. 544 * @return EINVAL if mode is NULL 545 */ 546 uint32_t lpddr4_setdbimode(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode); 547 548 /** 549 * Get the current value for the refresh rate (reading Refresh per 550 * command timing). 551 * @param[in] pD Driver state info specific to this instance. 552 * @param[in] fspNum Frequency set number 553 * @param[out] cycles Refresh rate (in cycles) 554 * @return CDN_EOK on success. 555 * @return EINVAL if rate is NULL 556 */ 557 uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles); 558 559 /** 560 * Set the refresh rate (writing Refresh per command timing). 561 * @param[in] pD Driver state info specific to this instance. 562 * @param[in] fspNum Frequency set number 563 * @param[in] cycles Refresh rate (in cycles) 564 * @return CDN_EOK on success. 565 * @return EINVAL if rate is NULL 566 */ 567 uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles); 568 569 /** 570 * Handle Refreshing per chip select 571 * @param[in] pD Driver state info specific to this instance. 572 * @param[in] trefInterval status 573 * @return CDN_EOK on success. 574 * @return EINVAL if chipSelect is invalid 575 */ 576 uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata* pd, const uint32_t trefinterval); 577 578 #endif /* LPDDR4_IF_H */ 579