1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012
4 * Altera Corporation <www.altera.com>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <log.h>
10 #include <asm-generic/io.h>
11 #include <dm.h>
12 #include <fdtdec.h>
13 #include <malloc.h>
14 #include <reset.h>
15 #include <spi.h>
16 #include <spi-mem.h>
17 #include <dm/device_compat.h>
18 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <linux/sizes.h>
21 #include "cadence_qspi.h"
22
23 #define CQSPI_STIG_READ 0
24 #define CQSPI_STIG_WRITE 1
25 #define CQSPI_READ 2
26 #define CQSPI_WRITE 3
27
cadence_spi_write_speed(struct udevice * bus,uint hz)28 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
29 {
30 struct cadence_spi_plat *plat = dev_get_plat(bus);
31 struct cadence_spi_priv *priv = dev_get_priv(bus);
32
33 cadence_qspi_apb_config_baudrate_div(priv->regbase,
34 plat->ref_clk_hz, hz);
35
36 /* Reconfigure delay timing if speed is changed. */
37 cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
38 plat->tshsl_ns, plat->tsd2d_ns,
39 plat->tchsh_ns, plat->tslch_ns);
40
41 return 0;
42 }
43
cadence_spi_read_id(void * reg_base,u8 len,u8 * idcode)44 static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
45 {
46 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
47 SPI_MEM_OP_NO_ADDR,
48 SPI_MEM_OP_NO_DUMMY,
49 SPI_MEM_OP_DATA_IN(len, idcode, 1));
50
51 return cadence_qspi_apb_command_read(reg_base, &op);
52 }
53
54 /* Calibration sequence to determine the read data capture delay register */
spi_calibration(struct udevice * bus,uint hz)55 static int spi_calibration(struct udevice *bus, uint hz)
56 {
57 struct cadence_spi_priv *priv = dev_get_priv(bus);
58 void *base = priv->regbase;
59 unsigned int idcode = 0, temp = 0;
60 int err = 0, i, range_lo = -1, range_hi = -1;
61
62 /* start with slowest clock (1 MHz) */
63 cadence_spi_write_speed(bus, 1000000);
64
65 /* configure the read data capture delay register to 0 */
66 cadence_qspi_apb_readdata_capture(base, 1, 0);
67
68 /* Enable QSPI */
69 cadence_qspi_apb_controller_enable(base);
70
71 /* read the ID which will be our golden value */
72 err = cadence_spi_read_id(base, 3, (u8 *)&idcode);
73 if (err) {
74 puts("SF: Calibration failed (read)\n");
75 return err;
76 }
77
78 /* use back the intended clock and find low range */
79 cadence_spi_write_speed(bus, hz);
80 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
81 /* Disable QSPI */
82 cadence_qspi_apb_controller_disable(base);
83
84 /* reconfigure the read data capture delay register */
85 cadence_qspi_apb_readdata_capture(base, 1, i);
86
87 /* Enable back QSPI */
88 cadence_qspi_apb_controller_enable(base);
89
90 /* issue a RDID to get the ID value */
91 err = cadence_spi_read_id(base, 3, (u8 *)&temp);
92 if (err) {
93 puts("SF: Calibration failed (read)\n");
94 return err;
95 }
96
97 /* search for range lo */
98 if (range_lo == -1 && temp == idcode) {
99 range_lo = i;
100 continue;
101 }
102
103 /* search for range hi */
104 if (range_lo != -1 && temp != idcode) {
105 range_hi = i - 1;
106 break;
107 }
108 range_hi = i;
109 }
110
111 if (range_lo == -1) {
112 puts("SF: Calibration failed (low range)\n");
113 return err;
114 }
115
116 /* Disable QSPI for subsequent initialization */
117 cadence_qspi_apb_controller_disable(base);
118
119 /* configure the final value for read data capture delay register */
120 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
121 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
122 (range_hi + range_lo) / 2, range_lo, range_hi);
123
124 /* just to ensure we do once only when speed or chip select change */
125 priv->qspi_calibrated_hz = hz;
126 priv->qspi_calibrated_cs = spi_chip_select(bus);
127
128 return 0;
129 }
130
cadence_spi_set_speed(struct udevice * bus,uint hz)131 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
132 {
133 struct cadence_spi_plat *plat = dev_get_plat(bus);
134 struct cadence_spi_priv *priv = dev_get_priv(bus);
135 int err;
136
137 if (hz > plat->max_hz)
138 hz = plat->max_hz;
139
140 /* Disable QSPI */
141 cadence_qspi_apb_controller_disable(priv->regbase);
142
143 /*
144 * Calibration required for different current SCLK speed, requested
145 * SCLK speed or chip select
146 */
147 if (priv->previous_hz != hz ||
148 priv->qspi_calibrated_hz != hz ||
149 priv->qspi_calibrated_cs != spi_chip_select(bus)) {
150 err = spi_calibration(bus, hz);
151 if (err)
152 return err;
153
154 /* prevent calibration run when same as previous request */
155 priv->previous_hz = hz;
156 }
157
158 /* Enable QSPI */
159 cadence_qspi_apb_controller_enable(priv->regbase);
160
161 debug("%s: speed=%d\n", __func__, hz);
162
163 return 0;
164 }
165
cadence_spi_probe(struct udevice * bus)166 static int cadence_spi_probe(struct udevice *bus)
167 {
168 struct cadence_spi_plat *plat = dev_get_plat(bus);
169 struct cadence_spi_priv *priv = dev_get_priv(bus);
170 struct clk clk;
171 int ret;
172
173 priv->regbase = plat->regbase;
174 priv->ahbbase = plat->ahbbase;
175
176 if (plat->ref_clk_hz == 0) {
177 ret = clk_get_by_index(bus, 0, &clk);
178 if (ret) {
179 #ifdef CONFIG_CQSPI_REF_CLK
180 plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
181 #else
182 return ret;
183 #endif
184 } else {
185 plat->ref_clk_hz = clk_get_rate(&clk);
186 clk_free(&clk);
187 if (IS_ERR_VALUE(plat->ref_clk_hz))
188 return plat->ref_clk_hz;
189 }
190 }
191
192 ret = reset_get_bulk(bus, &priv->resets);
193 if (ret)
194 dev_warn(bus, "Can't get reset: %d\n", ret);
195 else
196 reset_deassert_bulk(&priv->resets);
197
198 if (!priv->qspi_is_init) {
199 cadence_qspi_apb_controller_init(plat);
200 priv->qspi_is_init = 1;
201 }
202
203 return 0;
204 }
205
cadence_spi_remove(struct udevice * dev)206 static int cadence_spi_remove(struct udevice *dev)
207 {
208 struct cadence_spi_priv *priv = dev_get_priv(dev);
209
210 return reset_release_bulk(&priv->resets);
211 }
212
cadence_spi_set_mode(struct udevice * bus,uint mode)213 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
214 {
215 struct cadence_spi_plat *plat = dev_get_plat(bus);
216 struct cadence_spi_priv *priv = dev_get_priv(bus);
217
218 /* Disable QSPI */
219 cadence_qspi_apb_controller_disable(priv->regbase);
220
221 /* Set SPI mode */
222 cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
223
224 /* Enable Direct Access Controller */
225 if (plat->use_dac_mode)
226 cadence_qspi_apb_dac_mode_enable(priv->regbase);
227
228 /* Enable QSPI */
229 cadence_qspi_apb_controller_enable(priv->regbase);
230
231 return 0;
232 }
233
cadence_spi_mem_exec_op(struct spi_slave * spi,const struct spi_mem_op * op)234 static int cadence_spi_mem_exec_op(struct spi_slave *spi,
235 const struct spi_mem_op *op)
236 {
237 struct udevice *bus = spi->dev->parent;
238 struct cadence_spi_plat *plat = dev_get_plat(bus);
239 struct cadence_spi_priv *priv = dev_get_priv(bus);
240 void *base = priv->regbase;
241 int err = 0;
242 u32 mode;
243
244 /* Set Chip select */
245 cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
246 plat->is_decoded_cs);
247
248 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
249 if (!op->addr.nbytes)
250 mode = CQSPI_STIG_READ;
251 else
252 mode = CQSPI_READ;
253 } else {
254 if (!op->addr.nbytes || !op->data.buf.out)
255 mode = CQSPI_STIG_WRITE;
256 else
257 mode = CQSPI_WRITE;
258 }
259
260 switch (mode) {
261 case CQSPI_STIG_READ:
262 err = cadence_qspi_apb_command_read(base, op);
263 break;
264 case CQSPI_STIG_WRITE:
265 err = cadence_qspi_apb_command_write(base, op);
266 break;
267 case CQSPI_READ:
268 err = cadence_qspi_apb_read_setup(plat, op);
269 if (!err)
270 err = cadence_qspi_apb_read_execute(plat, op);
271 break;
272 case CQSPI_WRITE:
273 err = cadence_qspi_apb_write_setup(plat, op);
274 if (!err)
275 err = cadence_qspi_apb_write_execute(plat, op);
276 break;
277 default:
278 err = -1;
279 break;
280 }
281
282 return err;
283 }
284
cadence_spi_of_to_plat(struct udevice * bus)285 static int cadence_spi_of_to_plat(struct udevice *bus)
286 {
287 struct cadence_spi_plat *plat = dev_get_plat(bus);
288 ofnode subnode;
289
290 plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
291 plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
292 &plat->ahbsize);
293 plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
294 plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
295 plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
296 plat->trigger_address = dev_read_u32_default(bus,
297 "cdns,trigger-address",
298 0);
299 /* Use DAC mode only when MMIO window is at least 8M wide */
300 if (plat->ahbsize >= SZ_8M)
301 plat->use_dac_mode = true;
302
303 /* All other paramters are embedded in the child node */
304 subnode = dev_read_first_subnode(bus);
305 if (!ofnode_valid(subnode)) {
306 printf("Error: subnode with SPI flash config missing!\n");
307 return -ENODEV;
308 }
309
310 /* Use 500 KHz as a suitable default */
311 plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
312 500000);
313
314 /* Read other parameters from DT */
315 plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
316 plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
317 plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
318 200);
319 plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
320 255);
321 plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
322 plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
323
324 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
325 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
326 plat->page_size);
327
328 return 0;
329 }
330
331 static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
332 .exec_op = cadence_spi_mem_exec_op,
333 };
334
335 static const struct dm_spi_ops cadence_spi_ops = {
336 .set_speed = cadence_spi_set_speed,
337 .set_mode = cadence_spi_set_mode,
338 .mem_ops = &cadence_spi_mem_ops,
339 /*
340 * cs_info is not needed, since we require all chip selects to be
341 * in the device tree explicitly
342 */
343 };
344
345 static const struct udevice_id cadence_spi_ids[] = {
346 { .compatible = "cdns,qspi-nor" },
347 { .compatible = "ti,am654-ospi" },
348 { }
349 };
350
351 U_BOOT_DRIVER(cadence_spi) = {
352 .name = "cadence_spi",
353 .id = UCLASS_SPI,
354 .of_match = cadence_spi_ids,
355 .ops = &cadence_spi_ops,
356 .of_to_plat = cadence_spi_of_to_plat,
357 .plat_auto = sizeof(struct cadence_spi_plat),
358 .priv_auto = sizeof(struct cadence_spi_priv),
359 .probe = cadence_spi_probe,
360 .remove = cadence_spi_remove,
361 .flags = DM_FLAG_OS_PREPARE,
362 };
363