1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2001 Navin Boppuri / Prashant Patel
4 * <nboppuri@trinetcommunication.com>,
5 * <pmpatel@trinetcommunication.com>
6 * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
7 * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
8 */
9
10 /*
11 * MPC8xx CPM SPI interface.
12 *
13 * Parts of this code are probably not portable and/or specific to
14 * the board which I used for the tests. Please send fixes/complaints
15 * to wd@denx.de
16 *
17 */
18
19 #include <common.h>
20 #include <dm.h>
21 #include <mpc8xx.h>
22 #include <spi.h>
23 #include <linux/delay.h>
24
25 #include <asm/cpm_8xx.h>
26 #include <asm/io.h>
27
28 #define CPM_SPI_BASE_RX CPM_SPI_BASE
29 #define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
30
31 #define MAX_BUFFER 0x104
32
mpc8xx_spi_probe(struct udevice * dev)33 static int mpc8xx_spi_probe(struct udevice *dev)
34 {
35 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
36 cpm8xx_t __iomem *cp = &immr->im_cpm;
37 spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
38 cbd_t __iomem *tbdf, *rbdf;
39
40 /* Disable relocation */
41 out_be16(&spi->spi_rpbase, 0);
42
43 /* 1 */
44 /* ------------------------------------------------
45 * Initialize Port B SPI pins -> page 34-8 MPC860UM
46 * (we are only in Master Mode !)
47 * ------------------------------------------------ */
48
49 /* --------------------------------------------
50 * GPIO or per. Function
51 * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
52 * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
53 * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
54 * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
55 * -------------------------------------------- */
56 clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */
57
58 /* ----------------------------------------------
59 * In/Out or per. Function 0/1
60 * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
61 * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
62 * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
63 * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
64 * ---------------------------------------------- */
65 setbits_be32(&cp->cp_pbdir, 0x0000000F);
66
67 /* ----------------------------------------------
68 * open drain or active output
69 * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
70 * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
71 * PBODR[30] = 0 [0x00000002] -> active output: SPICLK
72 * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
73 * ---------------------------------------------- */
74
75 clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
76
77 /* Initialize the parameter ram.
78 * We need to make sure many things are initialized to zero
79 */
80 out_be32(&spi->spi_rstate, 0);
81 out_be32(&spi->spi_rdp, 0);
82 out_be16(&spi->spi_rbptr, 0);
83 out_be16(&spi->spi_rbc, 0);
84 out_be32(&spi->spi_rxtmp, 0);
85 out_be32(&spi->spi_tstate, 0);
86 out_be32(&spi->spi_tdp, 0);
87 out_be16(&spi->spi_tbptr, 0);
88 out_be16(&spi->spi_tbc, 0);
89 out_be32(&spi->spi_txtmp, 0);
90
91 /* 3 */
92 /* Set up the SPI parameters in the parameter ram */
93 out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX);
94 out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX);
95
96 /***********IMPORTANT******************/
97
98 /*
99 * Setting transmit and receive buffer descriptor pointers
100 * initially to rbase and tbase. Only the microcode patches
101 * documentation talks about initializing this pointer. This
102 * is missing from the sample I2C driver. If you dont
103 * initialize these pointers, the kernel hangs.
104 */
105 out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX);
106 out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX);
107
108 /* 4 */
109 /* Init SPI Tx + Rx Parameters */
110 while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
111 ;
112
113 out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) |
114 CPM_CR_FLG);
115 while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
116 ;
117
118 /* 5 */
119 /* Set SDMA configuration register */
120 out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
121
122 /* 6 */
123 /* Set to big endian. */
124 out_8(&spi->spi_tfcr, SMC_EB);
125 out_8(&spi->spi_rfcr, SMC_EB);
126
127 /* 7 */
128 /* Set maximum receive size. */
129 out_be16(&spi->spi_mrblr, MAX_BUFFER);
130
131 /* 8 + 9 */
132 /* tx and rx buffer descriptors */
133 tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
134 rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
135
136 clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
137 clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);
138
139 /* 10 + 11 */
140 out_8(&cp->cp_spim, 0); /* Mask all SPI events */
141 out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
142
143 return 0;
144 }
145
mpc8xx_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)146 static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
147 const void *dout, void *din, unsigned long flags)
148 {
149 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
150 cpm8xx_t __iomem *cp = &immr->im_cpm;
151 cbd_t __iomem *tbdf, *rbdf;
152 int tm;
153 size_t count = (bitlen + 7) / 8;
154
155 if (count > MAX_BUFFER)
156 return -EINVAL;
157
158 tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
159 rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
160
161 /* Set CS for device */
162 clrbits_be32(&cp->cp_pbdat, 0x0001);
163
164 /* Setting tx bd status and data length */
165 out_be32(&tbdf->cbd_bufaddr, (ulong)dout);
166 out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
167 out_be16(&tbdf->cbd_datlen, count);
168
169 /* Setting rx bd status and data length */
170 out_be32(&rbdf->cbd_bufaddr, (ulong)din);
171 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
172 out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
173
174 clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
175 SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8));
176 out_8(&cp->cp_spim, 0); /* Mask all SPI events */
177 out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
178
179 /* start spi transfer */
180 setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */
181
182 /* --------------------------------
183 * Wait for SPI transmit to get out
184 * or time out (1 second = 1000 ms)
185 * -------------------------------- */
186 for (tm = 0; tm < 1000; ++tm) {
187 if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
188 break;
189 if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
190 break;
191 udelay(1000);
192 }
193 if (tm >= 1000)
194 printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
195
196 /* Clear CS for device */
197 setbits_be32(&cp->cp_pbdat, 0x0001);
198
199 return count;
200 }
201
202 static const struct dm_spi_ops mpc8xx_spi_ops = {
203 .xfer = mpc8xx_spi_xfer,
204 };
205
206 static const struct udevice_id mpc8xx_spi_ids[] = {
207 { .compatible = "fsl,mpc8xx-spi" },
208 { }
209 };
210
211 U_BOOT_DRIVER(mpc8xx_spi) = {
212 .name = "mpc8xx_spi",
213 .id = UCLASS_SPI,
214 .of_match = mpc8xx_spi_ids,
215 .ops = &mpc8xx_spi_ops,
216 .probe = mpc8xx_spi_probe,
217 };
218