1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * NXP FlexSPI(FSPI) controller driver.
4 *
5 * Copyright (c) 2019 Michael Walle <michael@walle.cc>
6 * Copyright (c) 2019 NXP
7 *
8 * This driver was originally ported from the linux kernel v5.4-rc3, which had
9 * the following notes:
10 *
11 * FlexSPI is a flexsible SPI host controller which supports two SPI
12 * channels and up to 4 external devices. Each channel supports
13 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
14 * data lines).
15 *
16 * FlexSPI controller is driven by the LUT(Look-up Table) registers
17 * LUT registers are a look-up-table for sequences of instructions.
18 * A valid sequence consists of four LUT registers.
19 * Maximum 32 LUT sequences can be programmed simultaneously.
20 *
21 * LUTs are being created at run-time based on the commands passed
22 * from the spi-mem framework, thus using single LUT index.
23 *
24 * Software triggered Flash read/write access by IP Bus.
25 *
26 * Memory mapped read access by AHB Bus.
27 *
28 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
29 *
30 * Author:
31 * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
32 * Boris Brezillon <bbrezillon@kernel.org>
33 * Frieder Schrempf <frieder.schrempf@kontron.de>
34 */
35
36 #include <common.h>
37 #include <clk.h>
38 #include <dm.h>
39 #include <dm/device_compat.h>
40 #include <malloc.h>
41 #include <spi.h>
42 #include <spi-mem.h>
43 #include <asm/io.h>
44 #include <linux/bitops.h>
45 #include <linux/kernel.h>
46 #include <linux/sizes.h>
47 #include <linux/iopoll.h>
48 #include <linux/bug.h>
49 #include <linux/err.h>
50
51 /*
52 * The driver only uses one single LUT entry, that is updated on
53 * each call of exec_op(). Index 0 is preset at boot with a basic
54 * read operation, so let's use the last entry (31).
55 */
56 #define SEQID_LUT 31
57
58 /* Registers used by the driver */
59 #define FSPI_MCR0 0x00
60 #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
61 #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
62 #define FSPI_MCR0_LEARN_EN BIT(15)
63 #define FSPI_MCR0_SCRFRUN_EN BIT(14)
64 #define FSPI_MCR0_OCTCOMB_EN BIT(13)
65 #define FSPI_MCR0_DOZE_EN BIT(12)
66 #define FSPI_MCR0_HSEN BIT(11)
67 #define FSPI_MCR0_SERCLKDIV BIT(8)
68 #define FSPI_MCR0_ATDF_EN BIT(7)
69 #define FSPI_MCR0_ARDF_EN BIT(6)
70 #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
71 #define FSPI_MCR0_END_CFG(x) ((x) << 2)
72 #define FSPI_MCR0_MDIS BIT(1)
73 #define FSPI_MCR0_SWRST BIT(0)
74
75 #define FSPI_MCR1 0x04
76 #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
77 #define FSPI_MCR1_AHB_TIMEOUT(x) (x)
78
79 #define FSPI_MCR2 0x08
80 #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
81 #define FSPI_MCR2_SAMEDEVICEEN BIT(15)
82 #define FSPI_MCR2_CLRLRPHS BIT(14)
83 #define FSPI_MCR2_ABRDATSZ BIT(8)
84 #define FSPI_MCR2_ABRLEARN BIT(7)
85 #define FSPI_MCR2_ABR_READ BIT(6)
86 #define FSPI_MCR2_ABRWRITE BIT(5)
87 #define FSPI_MCR2_ABRDUMMY BIT(4)
88 #define FSPI_MCR2_ABR_MODE BIT(3)
89 #define FSPI_MCR2_ABRCADDR BIT(2)
90 #define FSPI_MCR2_ABRRADDR BIT(1)
91 #define FSPI_MCR2_ABR_CMD BIT(0)
92
93 #define FSPI_AHBCR 0x0c
94 #define FSPI_AHBCR_RDADDROPT BIT(6)
95 #define FSPI_AHBCR_PREF_EN BIT(5)
96 #define FSPI_AHBCR_BUFF_EN BIT(4)
97 #define FSPI_AHBCR_CACH_EN BIT(3)
98 #define FSPI_AHBCR_CLRTXBUF BIT(2)
99 #define FSPI_AHBCR_CLRRXBUF BIT(1)
100 #define FSPI_AHBCR_PAR_EN BIT(0)
101
102 #define FSPI_INTEN 0x10
103 #define FSPI_INTEN_SCLKSBWR BIT(9)
104 #define FSPI_INTEN_SCLKSBRD BIT(8)
105 #define FSPI_INTEN_DATALRNFL BIT(7)
106 #define FSPI_INTEN_IPTXWE BIT(6)
107 #define FSPI_INTEN_IPRXWA BIT(5)
108 #define FSPI_INTEN_AHBCMDERR BIT(4)
109 #define FSPI_INTEN_IPCMDERR BIT(3)
110 #define FSPI_INTEN_AHBCMDGE BIT(2)
111 #define FSPI_INTEN_IPCMDGE BIT(1)
112 #define FSPI_INTEN_IPCMDDONE BIT(0)
113
114 #define FSPI_INTR 0x14
115 #define FSPI_INTR_SCLKSBWR BIT(9)
116 #define FSPI_INTR_SCLKSBRD BIT(8)
117 #define FSPI_INTR_DATALRNFL BIT(7)
118 #define FSPI_INTR_IPTXWE BIT(6)
119 #define FSPI_INTR_IPRXWA BIT(5)
120 #define FSPI_INTR_AHBCMDERR BIT(4)
121 #define FSPI_INTR_IPCMDERR BIT(3)
122 #define FSPI_INTR_AHBCMDGE BIT(2)
123 #define FSPI_INTR_IPCMDGE BIT(1)
124 #define FSPI_INTR_IPCMDDONE BIT(0)
125
126 #define FSPI_LUTKEY 0x18
127 #define FSPI_LUTKEY_VALUE 0x5AF05AF0
128
129 #define FSPI_LCKCR 0x1C
130
131 #define FSPI_LCKER_LOCK 0x1
132 #define FSPI_LCKER_UNLOCK 0x2
133
134 #define FSPI_BUFXCR_INVALID_MSTRID 0xE
135 #define FSPI_AHBRX_BUF0CR0 0x20
136 #define FSPI_AHBRX_BUF1CR0 0x24
137 #define FSPI_AHBRX_BUF2CR0 0x28
138 #define FSPI_AHBRX_BUF3CR0 0x2C
139 #define FSPI_AHBRX_BUF4CR0 0x30
140 #define FSPI_AHBRX_BUF5CR0 0x34
141 #define FSPI_AHBRX_BUF6CR0 0x38
142 #define FSPI_AHBRX_BUF7CR0 0x3C
143 #define FSPI_AHBRXBUF0CR7_PREF BIT(31)
144
145 #define FSPI_AHBRX_BUF0CR1 0x40
146 #define FSPI_AHBRX_BUF1CR1 0x44
147 #define FSPI_AHBRX_BUF2CR1 0x48
148 #define FSPI_AHBRX_BUF3CR1 0x4C
149 #define FSPI_AHBRX_BUF4CR1 0x50
150 #define FSPI_AHBRX_BUF5CR1 0x54
151 #define FSPI_AHBRX_BUF6CR1 0x58
152 #define FSPI_AHBRX_BUF7CR1 0x5C
153
154 #define FSPI_FLSHA1CR0 0x60
155 #define FSPI_FLSHA2CR0 0x64
156 #define FSPI_FLSHB1CR0 0x68
157 #define FSPI_FLSHB2CR0 0x6C
158 #define FSPI_FLSHXCR0_SZ_KB 10
159 #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
160
161 #define FSPI_FLSHA1CR1 0x70
162 #define FSPI_FLSHA2CR1 0x74
163 #define FSPI_FLSHB1CR1 0x78
164 #define FSPI_FLSHB2CR1 0x7C
165 #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
166 #define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
167 #define FSPI_FLSHXCR1_WA BIT(10)
168 #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
169 #define FSPI_FLSHXCR1_TCSS(x) (x)
170
171 #define FSPI_FLSHA1CR2 0x80
172 #define FSPI_FLSHA2CR2 0x84
173 #define FSPI_FLSHB1CR2 0x88
174 #define FSPI_FLSHB2CR2 0x8C
175 #define FSPI_FLSHXCR2_CLRINSP BIT(24)
176 #define FSPI_FLSHXCR2_AWRWAIT BIT(16)
177 #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
178 #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
179 #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
180 #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
181
182 #define FSPI_IPCR0 0xA0
183
184 #define FSPI_IPCR1 0xA4
185 #define FSPI_IPCR1_IPAREN BIT(31)
186 #define FSPI_IPCR1_SEQNUM_SHIFT 24
187 #define FSPI_IPCR1_SEQID_SHIFT 16
188 #define FSPI_IPCR1_IDATSZ(x) (x)
189
190 #define FSPI_IPCMD 0xB0
191 #define FSPI_IPCMD_TRG BIT(0)
192
193 #define FSPI_DLPR 0xB4
194
195 #define FSPI_IPRXFCR 0xB8
196 #define FSPI_IPRXFCR_CLR BIT(0)
197 #define FSPI_IPRXFCR_DMA_EN BIT(1)
198 #define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
199
200 #define FSPI_IPTXFCR 0xBC
201 #define FSPI_IPTXFCR_CLR BIT(0)
202 #define FSPI_IPTXFCR_DMA_EN BIT(1)
203 #define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
204
205 #define FSPI_DLLACR 0xC0
206 #define FSPI_DLLACR_OVRDEN BIT(8)
207
208 #define FSPI_DLLBCR 0xC4
209 #define FSPI_DLLBCR_OVRDEN BIT(8)
210
211 #define FSPI_STS0 0xE0
212 #define FSPI_STS0_DLPHB(x) ((x) << 8)
213 #define FSPI_STS0_DLPHA(x) ((x) << 4)
214 #define FSPI_STS0_CMD_SRC(x) ((x) << 2)
215 #define FSPI_STS0_ARB_IDLE BIT(1)
216 #define FSPI_STS0_SEQ_IDLE BIT(0)
217
218 #define FSPI_STS1 0xE4
219 #define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
220 #define FSPI_STS1_IP_ERRID(x) ((x) << 16)
221 #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
222 #define FSPI_STS1_AHB_ERRID(x) (x)
223
224 #define FSPI_AHBSPNST 0xEC
225 #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
226 #define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
227 #define FSPI_AHBSPNST_ACTIVE BIT(0)
228
229 #define FSPI_IPRXFSTS 0xF0
230 #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
231 #define FSPI_IPRXFSTS_FILL(x) (x)
232
233 #define FSPI_IPTXFSTS 0xF4
234 #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
235 #define FSPI_IPTXFSTS_FILL(x) (x)
236
237 #define FSPI_RFDR 0x100
238 #define FSPI_TFDR 0x180
239
240 #define FSPI_LUT_BASE 0x200
241 #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
242 #define FSPI_LUT_REG(idx) \
243 (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
244
245 /* register map end */
246
247 /* Instruction set for the LUT register. */
248 #define LUT_STOP 0x00
249 #define LUT_CMD 0x01
250 #define LUT_ADDR 0x02
251 #define LUT_CADDR_SDR 0x03
252 #define LUT_MODE 0x04
253 #define LUT_MODE2 0x05
254 #define LUT_MODE4 0x06
255 #define LUT_MODE8 0x07
256 #define LUT_NXP_WRITE 0x08
257 #define LUT_NXP_READ 0x09
258 #define LUT_LEARN_SDR 0x0A
259 #define LUT_DATSZ_SDR 0x0B
260 #define LUT_DUMMY 0x0C
261 #define LUT_DUMMY_RWDS_SDR 0x0D
262 #define LUT_JMP_ON_CS 0x1F
263 #define LUT_CMD_DDR 0x21
264 #define LUT_ADDR_DDR 0x22
265 #define LUT_CADDR_DDR 0x23
266 #define LUT_MODE_DDR 0x24
267 #define LUT_MODE2_DDR 0x25
268 #define LUT_MODE4_DDR 0x26
269 #define LUT_MODE8_DDR 0x27
270 #define LUT_WRITE_DDR 0x28
271 #define LUT_READ_DDR 0x29
272 #define LUT_LEARN_DDR 0x2A
273 #define LUT_DATSZ_DDR 0x2B
274 #define LUT_DUMMY_DDR 0x2C
275 #define LUT_DUMMY_RWDS_DDR 0x2D
276
277 /*
278 * Calculate number of required PAD bits for LUT register.
279 *
280 * The pad stands for the number of IO lines [0:7].
281 * For example, the octal read needs eight IO lines,
282 * so you should use LUT_PAD(8). This macro
283 * returns 3 i.e. use eight (2^3) IP lines for read.
284 */
285 #define LUT_PAD(x) (fls(x) - 1)
286
287 /*
288 * Macro for constructing the LUT entries with the following
289 * register layout:
290 *
291 * ---------------------------------------------------
292 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
293 * ---------------------------------------------------
294 */
295 #define PAD_SHIFT 8
296 #define INSTR_SHIFT 10
297 #define OPRND_SHIFT 16
298
299 /* Macros for constructing the LUT register. */
300 #define LUT_DEF(idx, ins, pad, opr) \
301 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
302 (opr)) << (((idx) % 2) * OPRND_SHIFT))
303
304 #define POLL_TOUT 5000
305 #define NXP_FSPI_MAX_CHIPSELECT 4
306
307 struct nxp_fspi_devtype_data {
308 unsigned int rxfifo;
309 unsigned int txfifo;
310 unsigned int ahb_buf_size;
311 unsigned int quirks;
312 bool little_endian;
313 };
314
315 static const struct nxp_fspi_devtype_data lx2160a_data = {
316 .rxfifo = SZ_512, /* (64 * 64 bits) */
317 .txfifo = SZ_1K, /* (128 * 64 bits) */
318 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
319 .quirks = 0,
320 .little_endian = true, /* little-endian */
321 };
322
323 static const struct nxp_fspi_devtype_data imx8mm_data = {
324 .rxfifo = SZ_512, /* (64 * 64 bits) */
325 .txfifo = SZ_1K, /* (128 * 64 bits) */
326 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
327 .quirks = 0,
328 .little_endian = true, /* little-endian */
329 };
330
331 struct nxp_fspi {
332 struct udevice *dev;
333 void __iomem *iobase;
334 void __iomem *ahb_addr;
335 u32 memmap_phy;
336 u32 memmap_phy_size;
337 struct clk clk, clk_en;
338 const struct nxp_fspi_devtype_data *devtype_data;
339 };
340
341 /*
342 * R/W functions for big- or little-endian registers:
343 * The FSPI controller's endianness is independent of
344 * the CPU core's endianness. So far, although the CPU
345 * core is little-endian the FSPI controller can use
346 * big-endian or little-endian.
347 */
fspi_writel(struct nxp_fspi * f,u32 val,void __iomem * addr)348 static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
349 {
350 if (f->devtype_data->little_endian)
351 out_le32(addr, val);
352 else
353 out_be32(addr, val);
354 }
355
fspi_readl(struct nxp_fspi * f,void __iomem * addr)356 static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
357 {
358 if (f->devtype_data->little_endian)
359 return in_le32(addr);
360 else
361 return in_be32(addr);
362 }
363
nxp_fspi_check_buswidth(struct nxp_fspi * f,u8 width)364 static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
365 {
366 switch (width) {
367 case 1:
368 case 2:
369 case 4:
370 case 8:
371 return 0;
372 }
373
374 return -ENOTSUPP;
375 }
376
nxp_fspi_supports_op(struct spi_slave * slave,const struct spi_mem_op * op)377 static bool nxp_fspi_supports_op(struct spi_slave *slave,
378 const struct spi_mem_op *op)
379 {
380 struct nxp_fspi *f;
381 struct udevice *bus;
382 int ret;
383
384 bus = slave->dev->parent;
385 f = dev_get_priv(bus);
386
387 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
388
389 if (op->addr.nbytes)
390 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
391
392 if (op->dummy.nbytes)
393 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
394
395 if (op->data.nbytes)
396 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
397
398 if (ret)
399 return false;
400
401 /*
402 * The number of address bytes should be equal to or less than 4 bytes.
403 */
404 if (op->addr.nbytes > 4)
405 return false;
406
407 /*
408 * If requested address value is greater than controller assigned
409 * memory mapped space, return error as it didn't fit in the range
410 * of assigned address space.
411 */
412 if (op->addr.val >= f->memmap_phy_size)
413 return false;
414
415 /* Max 64 dummy clock cycles supported */
416 if (op->dummy.buswidth &&
417 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
418 return false;
419
420 /* Max data length, check controller limits and alignment */
421 if (op->data.dir == SPI_MEM_DATA_IN &&
422 (op->data.nbytes > f->devtype_data->ahb_buf_size ||
423 (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
424 !IS_ALIGNED(op->data.nbytes, 8))))
425 return false;
426
427 if (op->data.dir == SPI_MEM_DATA_OUT &&
428 op->data.nbytes > f->devtype_data->txfifo)
429 return false;
430
431 return true;
432 }
433
434 /* Instead of busy looping invoke readl_poll_sleep_timeout functionality. */
fspi_readl_poll_tout(struct nxp_fspi * f,void __iomem * base,u32 mask,u32 delay_us,u32 timeout_us,bool c)435 static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
436 u32 mask, u32 delay_us,
437 u32 timeout_us, bool c)
438 {
439 u32 reg;
440
441 if (!f->devtype_data->little_endian)
442 mask = (u32)cpu_to_be32(mask);
443
444 if (c)
445 return readl_poll_sleep_timeout(base, reg, (reg & mask),
446 delay_us, timeout_us);
447 else
448 return readl_poll_sleep_timeout(base, reg, !(reg & mask),
449 delay_us, timeout_us);
450 }
451
452 /*
453 * If the slave device content being changed by Write/Erase, need to
454 * invalidate the AHB buffer. This can be achieved by doing the reset
455 * of controller after setting MCR0[SWRESET] bit.
456 */
nxp_fspi_invalid(struct nxp_fspi * f)457 static inline void nxp_fspi_invalid(struct nxp_fspi *f)
458 {
459 u32 reg;
460 int ret;
461
462 reg = fspi_readl(f, f->iobase + FSPI_MCR0);
463 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
464
465 /* w1c register, wait unit clear */
466 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
467 FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
468 WARN_ON(ret);
469 }
470
nxp_fspi_prepare_lut(struct nxp_fspi * f,const struct spi_mem_op * op)471 static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
472 const struct spi_mem_op *op)
473 {
474 void __iomem *base = f->iobase;
475 u32 lutval[4] = {};
476 int lutidx = 1, i;
477
478 /* cmd */
479 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
480 op->cmd.opcode);
481
482 /* addr bytes */
483 if (op->addr.nbytes) {
484 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
485 LUT_PAD(op->addr.buswidth),
486 op->addr.nbytes * 8);
487 lutidx++;
488 }
489
490 /* dummy bytes, if needed */
491 if (op->dummy.nbytes) {
492 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
493 /*
494 * Due to FlexSPI controller limitation number of PAD for dummy
495 * buswidth needs to be programmed as equal to data buswidth.
496 */
497 LUT_PAD(op->data.buswidth),
498 op->dummy.nbytes * 8 /
499 op->dummy.buswidth);
500 lutidx++;
501 }
502
503 /* read/write data bytes */
504 if (op->data.nbytes) {
505 lutval[lutidx / 2] |= LUT_DEF(lutidx,
506 op->data.dir == SPI_MEM_DATA_IN ?
507 LUT_NXP_READ : LUT_NXP_WRITE,
508 LUT_PAD(op->data.buswidth),
509 0);
510 lutidx++;
511 }
512
513 /* stop condition. */
514 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
515
516 /* unlock LUT */
517 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
518 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
519
520 /* fill LUT */
521 for (i = 0; i < ARRAY_SIZE(lutval); i++)
522 fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
523
524 dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
525 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
526
527 /* lock LUT */
528 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
529 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
530 }
531
532 #if CONFIG_IS_ENABLED(CLK)
nxp_fspi_clk_prep_enable(struct nxp_fspi * f)533 static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
534 {
535 int ret;
536
537 ret = clk_enable(&f->clk_en);
538 if (ret)
539 return ret;
540
541 ret = clk_enable(&f->clk);
542 if (ret) {
543 clk_disable(&f->clk_en);
544 return ret;
545 }
546
547 return 0;
548 }
549
nxp_fspi_clk_disable_unprep(struct nxp_fspi * f)550 static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
551 {
552 clk_disable(&f->clk);
553 clk_disable(&f->clk_en);
554 }
555 #endif
556
557 /*
558 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
559 * register and start base address of the slave device.
560 *
561 * (Higher address)
562 * -------- <-- FLSHB2CR0
563 * | B2 |
564 * | |
565 * B2 start address --> -------- <-- FLSHB1CR0
566 * | B1 |
567 * | |
568 * B1 start address --> -------- <-- FLSHA2CR0
569 * | A2 |
570 * | |
571 * A2 start address --> -------- <-- FLSHA1CR0
572 * | A1 |
573 * | |
574 * A1 start address --> -------- (Lower address)
575 *
576 *
577 * Start base address defines the starting address range for given CS and
578 * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
579 *
580 * But, different targets are having different combinations of number of CS,
581 * some targets only have single CS or two CS covering controller's full
582 * memory mapped space area.
583 * Thus, implementation is being done as independent of the size and number
584 * of the connected slave device.
585 * Assign controller memory mapped space size as the size to the connected
586 * slave device.
587 * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
588 * chip-select Flash configuration register.
589 *
590 * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
591 * memory mapped size of the controller.
592 * Value for rest of the CS FLSHxxCR0 register would be zero.
593 *
594 */
nxp_fspi_select_mem(struct nxp_fspi * f,int chip_select)595 static void nxp_fspi_select_mem(struct nxp_fspi *f, int chip_select)
596 {
597 u64 size_kb;
598
599 /* Reset FLSHxxCR0 registers */
600 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
601 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
602 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
603 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
604
605 /* Assign controller memory mapped space as size, KBytes, of flash. */
606 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
607
608 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
609 4 * chip_select);
610
611 dev_dbg(f->dev, "Slave device [CS:%x] selected\n", chip_select);
612 }
613
nxp_fspi_read_ahb(struct nxp_fspi * f,const struct spi_mem_op * op)614 static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
615 {
616 u32 len = op->data.nbytes;
617
618 /* Read out the data directly from the AHB buffer. */
619 memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len);
620 }
621
nxp_fspi_fill_txfifo(struct nxp_fspi * f,const struct spi_mem_op * op)622 static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
623 const struct spi_mem_op *op)
624 {
625 void __iomem *base = f->iobase;
626 int i, ret;
627 u8 *buf = (u8 *)op->data.buf.out;
628
629 /* clear the TX FIFO. */
630 fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
631
632 /*
633 * Default value of water mark level is 8 bytes, hence in single
634 * write request controller can write max 8 bytes of data.
635 */
636
637 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
638 /* Wait for TXFIFO empty */
639 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
640 FSPI_INTR_IPTXWE, 0,
641 POLL_TOUT, true);
642 WARN_ON(ret);
643
644 fspi_writel(f, *(u32 *)(buf + i), base + FSPI_TFDR);
645 fspi_writel(f, *(u32 *)(buf + i + 4), base + FSPI_TFDR + 4);
646 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
647 }
648
649 if (i < op->data.nbytes) {
650 u32 data = 0;
651 int j;
652 /* Wait for TXFIFO empty */
653 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
654 FSPI_INTR_IPTXWE, 0,
655 POLL_TOUT, true);
656 WARN_ON(ret);
657
658 for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
659 memcpy(&data, buf + i + j, 4);
660 fspi_writel(f, data, base + FSPI_TFDR + j);
661 }
662 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
663 }
664 }
665
nxp_fspi_read_rxfifo(struct nxp_fspi * f,const struct spi_mem_op * op)666 static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
667 const struct spi_mem_op *op)
668 {
669 void __iomem *base = f->iobase;
670 int i, ret;
671 int len = op->data.nbytes;
672 u8 *buf = (u8 *)op->data.buf.in;
673
674 /*
675 * Default value of water mark level is 8 bytes, hence in single
676 * read request controller can read max 8 bytes of data.
677 */
678 for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
679 /* Wait for RXFIFO available */
680 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
681 FSPI_INTR_IPRXWA, 0,
682 POLL_TOUT, true);
683 WARN_ON(ret);
684
685 *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
686 *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
687 /* move the FIFO pointer */
688 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
689 }
690
691 if (i < len) {
692 u32 tmp;
693 int size, j;
694
695 buf = op->data.buf.in + i;
696 /* Wait for RXFIFO available */
697 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
698 FSPI_INTR_IPRXWA, 0,
699 POLL_TOUT, true);
700 WARN_ON(ret);
701
702 len = op->data.nbytes - i;
703 for (j = 0; j < op->data.nbytes - i; j += 4) {
704 tmp = fspi_readl(f, base + FSPI_RFDR + j);
705 size = min(len, 4);
706 memcpy(buf + j, &tmp, size);
707 len -= size;
708 }
709 }
710
711 /* invalid the RXFIFO */
712 fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
713 /* move the FIFO pointer */
714 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
715 }
716
nxp_fspi_do_op(struct nxp_fspi * f,const struct spi_mem_op * op)717 static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
718 {
719 void __iomem *base = f->iobase;
720 int seqnum = 0;
721 int err = 0;
722 u32 reg;
723
724 reg = fspi_readl(f, base + FSPI_IPRXFCR);
725 /* invalid RXFIFO first */
726 reg &= ~FSPI_IPRXFCR_DMA_EN;
727 reg = reg | FSPI_IPRXFCR_CLR;
728 fspi_writel(f, reg, base + FSPI_IPRXFCR);
729
730 fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
731 /*
732 * Always start the sequence at the same index since we update
733 * the LUT at each exec_op() call. And also specify the DATA
734 * length, since it's has not been specified in the LUT.
735 */
736 fspi_writel(f, op->data.nbytes |
737 (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
738 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
739 base + FSPI_IPCR1);
740
741 /* Trigger the LUT now. */
742 fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
743
744 /* Wait for the completion. */
745 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
746 FSPI_STS0_ARB_IDLE, 1, 1000 * 1000, true);
747
748 /* Invoke IP data read, if request is of data read. */
749 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
750 nxp_fspi_read_rxfifo(f, op);
751
752 return err;
753 }
754
nxp_fspi_exec_op(struct spi_slave * slave,const struct spi_mem_op * op)755 static int nxp_fspi_exec_op(struct spi_slave *slave,
756 const struct spi_mem_op *op)
757 {
758 struct nxp_fspi *f;
759 struct udevice *bus;
760 int err = 0;
761
762 bus = slave->dev->parent;
763 f = dev_get_priv(bus);
764
765 /* Wait for controller being ready. */
766 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
767 FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
768 WARN_ON(err);
769
770 nxp_fspi_prepare_lut(f, op);
771 /*
772 * If we have large chunks of data, we read them through the AHB bus
773 * by accessing the mapped memory. In all other cases we use
774 * IP commands to access the flash.
775 */
776 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
777 op->data.dir == SPI_MEM_DATA_IN) {
778 nxp_fspi_read_ahb(f, op);
779 } else {
780 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
781 nxp_fspi_fill_txfifo(f, op);
782
783 err = nxp_fspi_do_op(f, op);
784 }
785
786 /* Invalidate the data in the AHB buffer. */
787 nxp_fspi_invalid(f);
788
789 return err;
790 }
791
nxp_fspi_adjust_op_size(struct spi_slave * slave,struct spi_mem_op * op)792 static int nxp_fspi_adjust_op_size(struct spi_slave *slave,
793 struct spi_mem_op *op)
794 {
795 struct nxp_fspi *f;
796 struct udevice *bus;
797
798 bus = slave->dev->parent;
799 f = dev_get_priv(bus);
800
801 if (op->data.dir == SPI_MEM_DATA_OUT) {
802 if (op->data.nbytes > f->devtype_data->txfifo)
803 op->data.nbytes = f->devtype_data->txfifo;
804 } else {
805 if (op->data.nbytes > f->devtype_data->ahb_buf_size)
806 op->data.nbytes = f->devtype_data->ahb_buf_size;
807 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
808 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
809 }
810
811 return 0;
812 }
813
nxp_fspi_default_setup(struct nxp_fspi * f)814 static int nxp_fspi_default_setup(struct nxp_fspi *f)
815 {
816 void __iomem *base = f->iobase;
817 int ret, i;
818 u32 reg;
819
820 #if CONFIG_IS_ENABLED(CLK)
821 /* disable and unprepare clock to avoid glitch pass to controller */
822 nxp_fspi_clk_disable_unprep(f);
823
824 /* the default frequency, we will change it later if necessary. */
825 ret = clk_set_rate(&f->clk, 20000000);
826 if (ret < 0)
827 return ret;
828
829 ret = nxp_fspi_clk_prep_enable(f);
830 if (ret)
831 return ret;
832 #endif
833
834 /* Reset the module */
835 /* w1c register, wait unit clear */
836 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
837 FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
838 WARN_ON(ret);
839
840 /* Disable the module */
841 fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
842
843 /* Reset the DLL register to default value */
844 fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
845 fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
846
847 /* enable module */
848 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF),
849 base + FSPI_MCR0);
850
851 /*
852 * Disable same device enable bit and configure all slave devices
853 * independently.
854 */
855 reg = fspi_readl(f, f->iobase + FSPI_MCR2);
856 reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
857 fspi_writel(f, reg, base + FSPI_MCR2);
858
859 /* AHB configuration for access buffer 0~7. */
860 for (i = 0; i < 7; i++)
861 fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
862
863 /*
864 * Set ADATSZ with the maximum AHB buffer size to improve the read
865 * performance.
866 */
867 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
868 FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
869
870 /* prefetch and no start address alignment limitation */
871 fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
872 base + FSPI_AHBCR);
873
874 /* AHB Read - Set lut sequence ID for all CS. */
875 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
876 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
877 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
878 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
879
880 return 0;
881 }
882
nxp_fspi_probe(struct udevice * bus)883 static int nxp_fspi_probe(struct udevice *bus)
884 {
885 struct nxp_fspi *f = dev_get_priv(bus);
886
887 f->devtype_data =
888 (struct nxp_fspi_devtype_data *)dev_get_driver_data(bus);
889 nxp_fspi_default_setup(f);
890
891 return 0;
892 }
893
nxp_fspi_claim_bus(struct udevice * dev)894 static int nxp_fspi_claim_bus(struct udevice *dev)
895 {
896 struct nxp_fspi *f;
897 struct udevice *bus;
898 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
899
900 bus = dev->parent;
901 f = dev_get_priv(bus);
902
903 nxp_fspi_select_mem(f, slave_plat->cs);
904
905 return 0;
906 }
907
nxp_fspi_set_speed(struct udevice * bus,uint speed)908 static int nxp_fspi_set_speed(struct udevice *bus, uint speed)
909 {
910 #if CONFIG_IS_ENABLED(CLK)
911 struct nxp_fspi *f = dev_get_priv(bus);
912 int ret;
913
914 nxp_fspi_clk_disable_unprep(f);
915
916 ret = clk_set_rate(&f->clk, speed);
917 if (ret < 0)
918 return ret;
919
920 ret = nxp_fspi_clk_prep_enable(f);
921 if (ret)
922 return ret;
923 #endif
924 return 0;
925 }
926
nxp_fspi_set_mode(struct udevice * bus,uint mode)927 static int nxp_fspi_set_mode(struct udevice *bus, uint mode)
928 {
929 /* Nothing to do */
930 return 0;
931 }
932
nxp_fspi_of_to_plat(struct udevice * bus)933 static int nxp_fspi_of_to_plat(struct udevice *bus)
934 {
935 struct nxp_fspi *f = dev_get_priv(bus);
936 #if CONFIG_IS_ENABLED(CLK)
937 int ret;
938 #endif
939
940 fdt_addr_t iobase;
941 fdt_addr_t iobase_size;
942 fdt_addr_t ahb_addr;
943 fdt_addr_t ahb_size;
944
945 f->dev = bus;
946
947 iobase = devfdt_get_addr_size_name(bus, "fspi_base", &iobase_size);
948 if (iobase == FDT_ADDR_T_NONE) {
949 dev_err(bus, "fspi_base regs missing\n");
950 return -ENODEV;
951 }
952 f->iobase = map_physmem(iobase, iobase_size, MAP_NOCACHE);
953
954 ahb_addr = devfdt_get_addr_size_name(bus, "fspi_mmap", &ahb_size);
955 if (ahb_addr == FDT_ADDR_T_NONE) {
956 dev_err(bus, "fspi_mmap regs missing\n");
957 return -ENODEV;
958 }
959 f->ahb_addr = map_physmem(ahb_addr, ahb_size, MAP_NOCACHE);
960 f->memmap_phy_size = ahb_size;
961
962 #if CONFIG_IS_ENABLED(CLK)
963 ret = clk_get_by_name(bus, "fspi_en", &f->clk_en);
964 if (ret) {
965 dev_err(bus, "failed to get fspi_en clock\n");
966 return ret;
967 }
968
969 ret = clk_get_by_name(bus, "fspi", &f->clk);
970 if (ret) {
971 dev_err(bus, "failed to get fspi clock\n");
972 return ret;
973 }
974 #endif
975
976 dev_dbg(bus, "iobase=<0x%llx>, ahb_addr=<0x%llx>\n", iobase, ahb_addr);
977
978 return 0;
979 }
980
981 static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
982 .adjust_op_size = nxp_fspi_adjust_op_size,
983 .supports_op = nxp_fspi_supports_op,
984 .exec_op = nxp_fspi_exec_op,
985 };
986
987 static const struct dm_spi_ops nxp_fspi_ops = {
988 .claim_bus = nxp_fspi_claim_bus,
989 .set_speed = nxp_fspi_set_speed,
990 .set_mode = nxp_fspi_set_mode,
991 .mem_ops = &nxp_fspi_mem_ops,
992 };
993
994 static const struct udevice_id nxp_fspi_ids[] = {
995 { .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
996 { .compatible = "nxp,imx8mm-fspi", .data = (ulong)&imx8mm_data, },
997 { }
998 };
999
1000 U_BOOT_DRIVER(nxp_fspi) = {
1001 .name = "nxp_fspi",
1002 .id = UCLASS_SPI,
1003 .of_match = nxp_fspi_ids,
1004 .ops = &nxp_fspi_ops,
1005 .of_to_plat = nxp_fspi_of_to_plat,
1006 .priv_auto = sizeof(struct nxp_fspi),
1007 .probe = nxp_fspi_probe,
1008 };
1009