1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Qualcomm SPMI bus driver
4 *
5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
6 *
7 * Loosely based on Little Kernel driver
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <fdtdec.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <dm/device_compat.h>
17 #include <spmi/spmi.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 /* PMIC Arbiter configuration registers */
22 #define PMIC_ARB_VERSION 0x0000
23 #define PMIC_ARB_VERSION_V2_MIN 0x20010000
24
25 #define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
26 #define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
27
28 #define SPMI_REG_CMD0 0x0
29 #define SPMI_REG_CONFIG 0x4
30 #define SPMI_REG_STATUS 0x8
31 #define SPMI_REG_WDATA 0x10
32 #define SPMI_REG_RDATA 0x18
33
34 #define SPMI_CMD_OPCODE_SHIFT 27
35 #define SPMI_CMD_SLAVE_ID_SHIFT 20
36 #define SPMI_CMD_ADDR_SHIFT 12
37 #define SPMI_CMD_ADDR_OFFSET_SHIFT 4
38 #define SPMI_CMD_BYTE_CNT_SHIFT 0
39
40 #define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
41 #define SPMI_CMD_EXT_REG_READ_LONG 0x01
42
43 #define SPMI_STATUS_DONE 0x1
44
45 #define SPMI_MAX_CHANNELS 128
46 #define SPMI_MAX_SLAVES 16
47 #define SPMI_MAX_PERIPH 256
48
49 struct msm_spmi_priv {
50 phys_addr_t arb_chnl; /* ARB channel mapping base */
51 phys_addr_t spmi_core; /* SPMI core */
52 phys_addr_t spmi_obs; /* SPMI observer */
53 /* SPMI channel map */
54 uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
55 };
56
msm_spmi_write(struct udevice * dev,int usid,int pid,int off,uint8_t val)57 static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
58 uint8_t val)
59 {
60 struct msm_spmi_priv *priv = dev_get_priv(dev);
61 unsigned channel;
62 uint32_t reg = 0;
63
64 if (usid >= SPMI_MAX_SLAVES)
65 return -EIO;
66 if (pid >= SPMI_MAX_PERIPH)
67 return -EIO;
68
69 channel = priv->channel_map[usid][pid];
70
71 /* Disable IRQ mode for the current channel*/
72 writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) +
73 SPMI_REG_CONFIG);
74
75 /* Write single byte */
76 writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
77
78 /* Prepare write command */
79 reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
80 reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
81 reg |= (pid << SPMI_CMD_ADDR_SHIFT);
82 reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
83 reg |= 1; /* byte count */
84
85 /* Send write command */
86 writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
87
88 /* Wait till CMD DONE status */
89 reg = 0;
90 while (!reg) {
91 reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) +
92 SPMI_REG_STATUS);
93 }
94
95 if (reg ^ SPMI_STATUS_DONE) {
96 printf("SPMI write failure.\n");
97 return -EIO;
98 }
99
100 return 0;
101 }
102
msm_spmi_read(struct udevice * dev,int usid,int pid,int off)103 static int msm_spmi_read(struct udevice *dev, int usid, int pid, int off)
104 {
105 struct msm_spmi_priv *priv = dev_get_priv(dev);
106 unsigned channel;
107 uint32_t reg = 0;
108
109 if (usid >= SPMI_MAX_SLAVES)
110 return -EIO;
111 if (pid >= SPMI_MAX_PERIPH)
112 return -EIO;
113
114 channel = priv->channel_map[usid][pid];
115
116 /* Disable IRQ mode for the current channel*/
117 writel(0x0, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
118
119 /* Prepare read command */
120 reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
121 reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
122 reg |= (pid << SPMI_CMD_ADDR_SHIFT);
123 reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
124 reg |= 1; /* byte count */
125
126 /* Request read */
127 writel(reg, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
128
129 /* Wait till CMD DONE status */
130 reg = 0;
131 while (!reg) {
132 reg = readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
133 SPMI_REG_STATUS);
134 }
135
136 if (reg ^ SPMI_STATUS_DONE) {
137 printf("SPMI read failure.\n");
138 return -EIO;
139 }
140
141 /* Read the data */
142 return readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
143 SPMI_REG_RDATA) & 0xFF;
144 }
145
146 static struct dm_spmi_ops msm_spmi_ops = {
147 .read = msm_spmi_read,
148 .write = msm_spmi_write,
149 };
150
msm_spmi_probe(struct udevice * dev)151 static int msm_spmi_probe(struct udevice *dev)
152 {
153 struct udevice *parent = dev->parent;
154 struct msm_spmi_priv *priv = dev_get_priv(dev);
155 int node = dev_of_offset(dev);
156 u32 hw_ver;
157 bool is_v1;
158 int i;
159
160 priv->arb_chnl = dev_read_addr(dev);
161 priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
162 dev_of_offset(parent), node, "reg", 1, NULL, false);
163 priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
164 dev_of_offset(parent), node, "reg", 2, NULL, false);
165
166 hw_ver = readl(priv->arb_chnl + PMIC_ARB_VERSION - 0x800);
167 is_v1 = (hw_ver < PMIC_ARB_VERSION_V2_MIN);
168
169 dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), hw_ver);
170
171 if (priv->arb_chnl == FDT_ADDR_T_NONE ||
172 priv->spmi_core == FDT_ADDR_T_NONE ||
173 priv->spmi_obs == FDT_ADDR_T_NONE)
174 return -EINVAL;
175
176 /* Scan peripherals connected to each SPMI channel */
177 for (i = 0; i < SPMI_MAX_PERIPH ; i++) {
178 uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
179 uint8_t slave_id = (periph & 0xf0000) >> 16;
180 uint8_t pid = (periph & 0xff00) >> 8;
181
182 priv->channel_map[slave_id][pid] = i;
183 }
184 return 0;
185 }
186
187 static const struct udevice_id msm_spmi_ids[] = {
188 { .compatible = "qcom,spmi-pmic-arb" },
189 { }
190 };
191
192 U_BOOT_DRIVER(msm_spmi) = {
193 .name = "msm_spmi",
194 .id = UCLASS_SPMI,
195 .of_match = msm_spmi_ids,
196 .ops = &msm_spmi_ops,
197 .probe = msm_spmi_probe,
198 .priv_auto = sizeof(struct msm_spmi_priv),
199 };
200