1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Amlogic Meson Video Processing Unit driver
4 *
5 * Copyright (c) 2018 BayLibre, SAS.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <asm/io.h>
12 #include <linux/bitfield.h>
13 #include <linux/bitops.h>
14
15 #include "meson_vpu.h"
16
17 /* OSDx_BLKx_CFG */
18 #define OSD_CANVAS_SEL 16
19
20 #define OSD_ENDIANNESS_LE BIT(15)
21 #define OSD_ENDIANNESS_BE (0)
22
23 #define OSD_BLK_MODE_422 (0x03 << 8)
24 #define OSD_BLK_MODE_16 (0x04 << 8)
25 #define OSD_BLK_MODE_32 (0x05 << 8)
26 #define OSD_BLK_MODE_24 (0x07 << 8)
27
28 #define OSD_OUTPUT_COLOR_RGB BIT(7)
29 #define OSD_OUTPUT_COLOR_YUV (0)
30
31 #define OSD_COLOR_MATRIX_32_RGBA (0x00 << 2)
32 #define OSD_COLOR_MATRIX_32_ARGB (0x01 << 2)
33 #define OSD_COLOR_MATRIX_32_ABGR (0x02 << 2)
34 #define OSD_COLOR_MATRIX_32_BGRA (0x03 << 2)
35
36 #define OSD_COLOR_MATRIX_24_RGB (0x00 << 2)
37
38 #define OSD_COLOR_MATRIX_16_RGB655 (0x00 << 2)
39 #define OSD_COLOR_MATRIX_16_RGB565 (0x04 << 2)
40
41 #define OSD_INTERLACE_ENABLED BIT(1)
42 #define OSD_INTERLACE_ODD BIT(0)
43 #define OSD_INTERLACE_EVEN (0)
44
45 /* OSDx_CTRL_STAT */
46 #define OSD_ENABLE BIT(21)
47 #define OSD_BLK0_ENABLE BIT(0)
48
49 #define OSD_GLOBAL_ALPHA_SHIFT 12
50
51 /* OSDx_CTRL_STAT2 */
52 #define OSD_REPLACE_EN BIT(14)
53 #define OSD_REPLACE_SHIFT 6
54
55 /*
56 * When the output is interlaced, the OSD must switch between
57 * each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0
58 * at each vsync.
59 * But the vertical scaler can provide such funtionnality if
60 * is configured for 2:1 scaling with interlace options enabled.
61 */
meson_vpp_setup_interlace_vscaler_osd1(struct meson_vpu_priv * priv,struct video_priv * uc_priv)62 static void meson_vpp_setup_interlace_vscaler_osd1(struct meson_vpu_priv *priv,
63 struct video_priv *uc_priv)
64 {
65 writel(BIT(3) /* Enable scaler */ |
66 BIT(2), /* Select OSD1 */
67 priv->io_base + _REG(VPP_OSD_SC_CTRL0));
68
69 writel(((uc_priv->xsize - 1) << 16) | (uc_priv->ysize - 1),
70 priv->io_base + _REG(VPP_OSD_SCI_WH_M1));
71 /* 2:1 scaling */
72 writel((0 << 16) | uc_priv->xsize,
73 priv->io_base + _REG(VPP_OSD_SCO_H_START_END));
74 writel(((0 >> 1) << 16) | (uc_priv->ysize >> 1),
75 priv->io_base + _REG(VPP_OSD_SCO_V_START_END));
76
77 /* 2:1 scaling values */
78 writel(BIT(16), priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));
79 writel(BIT(25), priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));
80
81 writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
82
83 writel((4 << 0) /* osd_vsc_bank_length */ |
84 (4 << 3) /* osd_vsc_top_ini_rcv_num0 */ |
85 (1 << 8) /* osd_vsc_top_rpt_p0_num0 */ |
86 (6 << 11) /* osd_vsc_bot_ini_rcv_num0 */ |
87 (2 << 16) /* osd_vsc_bot_rpt_p0_num0 */ |
88 BIT(23) /* osd_prog_interlace */ |
89 BIT(24), /* Enable vertical scaler */
90 priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
91 }
92
93 static void
meson_vpp_disable_interlace_vscaler_osd1(struct meson_vpu_priv * priv)94 meson_vpp_disable_interlace_vscaler_osd1(struct meson_vpu_priv *priv)
95 {
96 writel(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
97 writel(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
98 writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
99 }
100
meson_vpu_setup_plane(struct udevice * dev,bool is_interlaced)101 void meson_vpu_setup_plane(struct udevice *dev, bool is_interlaced)
102 {
103 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
104 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
105 struct meson_vpu_priv *priv = dev_get_priv(dev);
106 u32 osd1_ctrl_stat;
107 u32 osd1_blk0_cfg[5];
108 bool osd1_interlace;
109 unsigned int src_x1, src_x2, src_y1, src_y2;
110 unsigned int dest_x1, dest_x2, dest_y1, dest_y2;
111
112 dest_x1 = src_x1 = 0;
113 dest_x2 = src_x2 = uc_priv->xsize;
114 dest_y1 = src_y1 = 0;
115 dest_y2 = src_y2 = uc_priv->ysize;
116
117 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
118 /* VD1 Preblend vertical start/end */
119 writel(FIELD_PREP(GENMASK(11, 0), 2303),
120 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));
121
122 /* Setup Blender */
123 writel(uc_priv->xsize |
124 uc_priv->ysize << 16,
125 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
126
127 writel(0 << 16 |
128 (uc_priv->xsize - 1),
129 priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE));
130 writel(0 << 16 |
131 (uc_priv->ysize - 1),
132 priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE));
133 writel(uc_priv->xsize << 16 |
134 uc_priv->ysize,
135 priv->io_base + _REG(VPP_OUT_H_V_SIZE));
136 } else {
137 /* Enable VPP Postblend */
138 writel(uc_priv->xsize,
139 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
140
141 writel_bits(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
142 priv->io_base + _REG(VPP_MISC));
143 }
144
145 /* uc_plat->base is the framebuffer */
146
147 /* Enable OSD and BLK0, set max global alpha */
148 osd1_ctrl_stat = OSD_ENABLE | (0xFF << OSD_GLOBAL_ALPHA_SHIFT) |
149 OSD_BLK0_ENABLE;
150
151 /* Set up BLK0 to point to the right canvas */
152 osd1_blk0_cfg[0] = ((MESON_CANVAS_ID_OSD1 << OSD_CANVAS_SEL) |
153 OSD_ENDIANNESS_LE);
154
155 /* On GXBB, Use the old non-HDR RGB2YUV converter */
156 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
157 osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
158
159 /* For XRGB, replace the pixel's alpha by 0xFF */
160 writel_bits(OSD_REPLACE_EN, OSD_REPLACE_EN,
161 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
162 osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
163 OSD_COLOR_MATRIX_32_ARGB;
164
165 if (is_interlaced) {
166 osd1_interlace = true;
167 dest_y1 /= 2;
168 dest_y2 /= 2;
169 } else {
170 osd1_interlace = false;
171 }
172
173 /*
174 * The format of these registers is (x2 << 16 | x1),
175 * where x2 is exclusive.
176 * e.g. +30x1920 would be (1919 << 16) | 30
177 */
178 osd1_blk0_cfg[1] = ((src_x2 - 1) << 16) | src_x1;
179 osd1_blk0_cfg[2] = ((src_y2 - 1) << 16) | src_y1;
180 osd1_blk0_cfg[3] = ((dest_x2 - 1) << 16) | dest_x1;
181 osd1_blk0_cfg[4] = ((dest_y2 - 1) << 16) | dest_y1;
182
183 writel(osd1_ctrl_stat, priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
184 writel(osd1_blk0_cfg[0], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
185 writel(osd1_blk0_cfg[1], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1));
186 writel(osd1_blk0_cfg[2], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2));
187 writel(osd1_blk0_cfg[3], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3));
188 writel(osd1_blk0_cfg[4], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4));
189
190 /* If output is interlace, make use of the Scaler */
191 if (osd1_interlace)
192 meson_vpp_setup_interlace_vscaler_osd1(priv, uc_priv);
193 else
194 meson_vpp_disable_interlace_vscaler_osd1(priv);
195
196 meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
197 uc_plat->base, uc_priv->xsize * 4,
198 uc_priv->ysize, MESON_CANVAS_WRAP_NONE,
199 MESON_CANVAS_BLKMODE_LINEAR);
200
201 /* Enable OSD1 */
202 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
203 writel(((dest_x2 - 1) << 16) | dest_x1,
204 priv->io_base + _REG(VIU_OSD_BLEND_DIN0_SCOPE_H));
205 writel(((dest_y2 - 1) << 16) | dest_y1,
206 priv->io_base + _REG(VIU_OSD_BLEND_DIN0_SCOPE_V));
207 writel(uc_priv->xsize << 16 | uc_priv->ysize,
208 priv->io_base + _REG(VIU_OSD_BLEND_BLEND0_SIZE));
209 writel(uc_priv->xsize << 16 | uc_priv->ysize,
210 priv->io_base + _REG(VIU_OSD_BLEND_BLEND1_SIZE));
211 writel_bits(3 << 8, 3 << 8,
212 priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
213 } else
214 writel_bits(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
215 priv->io_base + _REG(VPP_MISC));
216 }
217