1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Amlogic Meson Video Processing Unit driver 4 * 5 * Copyright (c) 2018 BayLibre, SAS. 6 * Author: Neil Armstrong <narmstrong@baylibre.com> 7 */ 8 9 #ifndef __MESON_VPU_H__ 10 #define __MESON_VPU_H__ 11 12 #include <video.h> 13 #include "meson_registers.h" 14 15 struct display_timing; 16 struct udevice; 17 18 enum { 19 /* Maximum size we support */ 20 VPU_MAX_WIDTH = 3840, 21 VPU_MAX_HEIGHT = 2160, 22 VPU_MAX_LOG2_BPP = VIDEO_BPP32, 23 }; 24 25 enum vpu_compatible { 26 VPU_COMPATIBLE_GXBB = 0, 27 VPU_COMPATIBLE_GXL = 1, 28 VPU_COMPATIBLE_GXM = 2, 29 VPU_COMPATIBLE_G12A = 3, 30 }; 31 32 struct meson_vpu_priv { 33 struct udevice *dev; 34 void __iomem *io_base; 35 void __iomem *hhi_base; 36 void __iomem *dmc_base; 37 }; 38 39 bool meson_vpu_is_compatible(struct meson_vpu_priv *priv, 40 enum vpu_compatible family); 41 42 #define hhi_update_bits(offset, mask, value) \ 43 writel_bits(mask, value, priv->hhi_base + offset) 44 45 #define hhi_write(offset, value) \ 46 writel(value, priv->hhi_base + offset) 47 48 #define hhi_read(offset) \ 49 readl(priv->hhi_base + offset) 50 51 #define dmc_update_bits(offset, mask, value) \ 52 writel_bits(mask, value, priv->dmc_base + offset) 53 54 #define dmc_write(offset, value) \ 55 writel(value, priv->dmc_base + offset) 56 57 #define dmc_read(offset) \ 58 readl(priv->dmc_base + offset) 59 60 #define MESON_CANVAS_ID_OSD1 0x4e 61 62 /* Canvas configuration. */ 63 #define MESON_CANVAS_WRAP_NONE 0x00 64 #define MESON_CANVAS_WRAP_X 0x01 65 #define MESON_CANVAS_WRAP_Y 0x02 66 67 #define MESON_CANVAS_BLKMODE_LINEAR 0x00 68 #define MESON_CANVAS_BLKMODE_32x32 0x01 69 #define MESON_CANVAS_BLKMODE_64x64 0x02 70 71 void meson_canvas_setup(struct meson_vpu_priv *priv, 72 u32 canvas_index, u32 addr, 73 u32 stride, u32 height, 74 unsigned int wrap, 75 unsigned int blkmode); 76 77 /* Mux VIU/VPP to ENCI */ 78 #define MESON_VIU_VPP_MUX_ENCI 0x5 79 /* Mux VIU/VPP to ENCP */ 80 #define MESON_VIU_VPP_MUX_ENCP 0xA 81 82 void meson_vpp_setup_mux(struct meson_vpu_priv *priv, unsigned int mux); 83 void meson_vpu_init(struct udevice *dev); 84 void meson_vpu_setup_plane(struct udevice *dev, bool is_interlaced); 85 bool meson_venc_hdmi_supported_mode(const struct display_timing *mode); 86 void meson_vpu_setup_venc(struct udevice *dev, 87 const struct display_timing *mode, bool is_cvbs); 88 bool meson_vclk_dmt_supported_freq(struct meson_vpu_priv *priv, 89 unsigned int freq); 90 void meson_vpu_setup_vclk(struct udevice *dev, 91 const struct display_timing *mode, bool is_cvbs); 92 #endif 93