1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale i.MX23/i.MX28 LCDIF driver
4 *
5 * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
6 */
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <env.h>
11 #include <log.h>
12 #include <asm/cache.h>
13 #include <dm/device_compat.h>
14 #include <linux/delay.h>
15 #include <linux/errno.h>
16 #include <malloc.h>
17 #include <video.h>
18 #include <video_fb.h>
19
20 #include <asm/arch/clock.h>
21 #include <asm/arch/imx-regs.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/global_data.h>
24 #include <asm/mach-imx/dma.h>
25 #include <asm/io.h>
26
27 #include "videomodes.h"
28
29 #define PS2KHZ(ps) (1000000000UL / (ps))
30 #define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
31
32 #define BITS_PP 18
33 #define BYTES_PP 4
34
35 struct mxs_dma_desc desc;
36
37 /**
38 * mxsfb_system_setup() - Fine-tune LCDIF configuration
39 *
40 * This function is used to adjust the LCDIF configuration. This is usually
41 * needed when driving the controller in System-Mode to operate an 8080 or
42 * 6800 connected SmartLCD.
43 */
mxsfb_system_setup(void)44 __weak void mxsfb_system_setup(void)
45 {
46 }
47
48 /*
49 * ARIES M28EVK:
50 * setenv videomode
51 * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
52 * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
53 *
54 * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
55 * setenv videomode
56 * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
57 * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
58 */
59
mxs_lcd_init(struct udevice * dev,u32 fb_addr,struct display_timing * timings,int bpp)60 static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
61 struct display_timing *timings, int bpp)
62 {
63 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
64 const enum display_flags flags = timings->flags;
65 uint32_t word_len = 0, bus_width = 0;
66 uint8_t valid_data = 0;
67 uint32_t vdctrl0;
68
69 #if CONFIG_IS_ENABLED(CLK)
70 struct clk per_clk;
71 int ret;
72
73 ret = clk_get_by_name(dev, "per", &per_clk);
74 if (ret) {
75 dev_err(dev, "Failed to get mxs clk: %d\n", ret);
76 return;
77 }
78
79 ret = clk_set_rate(&per_clk, timings->pixelclock.typ);
80 if (ret < 0) {
81 dev_err(dev, "Failed to set mxs clk: %d\n", ret);
82 return;
83 }
84
85 ret = clk_enable(&per_clk);
86 if (ret < 0) {
87 dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
88 return;
89 }
90 #else
91 /* Kick in the LCDIF clock */
92 mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
93 #endif
94
95 /* Restart the LCDIF block */
96 mxs_reset_block(®s->hw_lcdif_ctrl_reg);
97
98 switch (bpp) {
99 case 24:
100 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
101 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
102 valid_data = 0x7;
103 break;
104 case 18:
105 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
106 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
107 valid_data = 0x7;
108 break;
109 case 16:
110 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
111 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
112 valid_data = 0xf;
113 break;
114 case 8:
115 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
116 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
117 valid_data = 0xf;
118 break;
119 }
120
121 writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
122 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
123 ®s->hw_lcdif_ctrl);
124
125 writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
126 ®s->hw_lcdif_ctrl1);
127
128 mxsfb_system_setup();
129
130 writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
131 timings->hactive.typ, ®s->hw_lcdif_transfer_count);
132
133 vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
134 LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
135 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
136 timings->vsync_len.typ;
137
138 if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
139 vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
140 if(flags & DISPLAY_FLAGS_VSYNC_HIGH)
141 vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
142 if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
143 vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
144 if(flags & DISPLAY_FLAGS_DE_HIGH)
145 vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
146
147 writel(vdctrl0, ®s->hw_lcdif_vdctrl0);
148 writel(timings->vback_porch.typ + timings->vfront_porch.typ +
149 timings->vsync_len.typ + timings->vactive.typ,
150 ®s->hw_lcdif_vdctrl1);
151 writel((timings->hsync_len.typ << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
152 (timings->hback_porch.typ + timings->hfront_porch.typ +
153 timings->hsync_len.typ + timings->hactive.typ),
154 ®s->hw_lcdif_vdctrl2);
155 writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
156 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
157 (timings->vback_porch.typ + timings->vsync_len.typ),
158 ®s->hw_lcdif_vdctrl3);
159 writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | timings->hactive.typ,
160 ®s->hw_lcdif_vdctrl4);
161
162 writel(fb_addr, ®s->hw_lcdif_cur_buf);
163 writel(fb_addr, ®s->hw_lcdif_next_buf);
164
165 /* Flush FIFO first */
166 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set);
167
168 #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
169 /* Sync signals ON */
170 setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
171 #endif
172
173 /* FIFO cleared */
174 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr);
175
176 /* RUN! */
177 writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
178 }
179
mxs_probe_common(struct udevice * dev,struct display_timing * timings,int bpp,u32 fb)180 static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
181 int bpp, u32 fb)
182 {
183 /* Start framebuffer */
184 mxs_lcd_init(dev, fb, timings, bpp);
185
186 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
187 /*
188 * If the LCD runs in system mode, the LCD refresh has to be triggered
189 * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
190 * having to set this bit manually after every single change in the
191 * framebuffer memory, we set up specially crafted circular DMA, which
192 * sets the RUN bit, then waits until it gets cleared and repeats this
193 * infinitelly. This way, we get smooth continuous updates of the LCD.
194 */
195 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
196
197 memset(&desc, 0, sizeof(struct mxs_dma_desc));
198 desc.address = (dma_addr_t)&desc;
199 desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
200 MXS_DMA_DESC_WAIT4END |
201 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
202 desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
203 desc.cmd.next = (uint32_t)&desc.cmd;
204
205 /* Execute the DMA chain. */
206 mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
207 #endif
208
209 return 0;
210 }
211
mxs_remove_common(u32 fb)212 static int mxs_remove_common(u32 fb)
213 {
214 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
215 int timeout = 1000000;
216
217 if (!fb)
218 return -EINVAL;
219
220 writel(fb, ®s->hw_lcdif_cur_buf_reg);
221 writel(fb, ®s->hw_lcdif_next_buf_reg);
222 writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
223 while (--timeout) {
224 if (readl(®s->hw_lcdif_ctrl1_reg) &
225 LCDIF_CTRL1_VSYNC_EDGE_IRQ)
226 break;
227 udelay(1);
228 }
229 mxs_reset_block((struct mxs_register_32 *)®s->hw_lcdif_ctrl_reg);
230
231 return 0;
232 }
233
234 #ifndef CONFIG_DM_VIDEO
235
236 static GraphicDevice panel;
237
lcdif_power_down(void)238 void lcdif_power_down(void)
239 {
240 mxs_remove_common(panel.frameAdrs);
241 }
242
video_hw_init(void)243 void *video_hw_init(void)
244 {
245 int bpp = -1;
246 int ret = 0;
247 char *penv;
248 void *fb = NULL;
249 struct ctfb_res_modes mode;
250 struct display_timing timings;
251
252 puts("Video: ");
253
254 /* Suck display configuration from "videomode" variable */
255 penv = env_get("videomode");
256 if (!penv) {
257 puts("MXSFB: 'videomode' variable not set!\n");
258 return NULL;
259 }
260
261 bpp = video_get_params(&mode, penv);
262
263 /* fill in Graphic device struct */
264 sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
265
266 panel.winSizeX = mode.xres;
267 panel.winSizeY = mode.yres;
268 panel.plnSizeX = mode.xres;
269 panel.plnSizeY = mode.yres;
270
271 switch (bpp) {
272 case 24:
273 case 18:
274 panel.gdfBytesPP = 4;
275 panel.gdfIndex = GDF_32BIT_X888RGB;
276 break;
277 case 16:
278 panel.gdfBytesPP = 2;
279 panel.gdfIndex = GDF_16BIT_565RGB;
280 break;
281 case 8:
282 panel.gdfBytesPP = 1;
283 panel.gdfIndex = GDF__8BIT_INDEX;
284 break;
285 default:
286 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
287 return NULL;
288 }
289
290 panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
291
292 /* Allocate framebuffer */
293 fb = memalign(ARCH_DMA_MINALIGN,
294 roundup(panel.memSize, ARCH_DMA_MINALIGN));
295 if (!fb) {
296 printf("MXSFB: Error allocating framebuffer!\n");
297 return NULL;
298 }
299
300 /* Wipe framebuffer */
301 memset(fb, 0, panel.memSize);
302
303 panel.frameAdrs = (u32)fb;
304
305 printf("%s\n", panel.modeIdent);
306
307 video_ctfb_mode_to_display_timing(&mode, &timings);
308
309 ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
310 if (ret)
311 goto dealloc_fb;
312
313 return (void *)&panel;
314
315 dealloc_fb:
316 free(fb);
317
318 return NULL;
319 }
320 #else /* ifndef CONFIG_DM_VIDEO */
321
mxs_of_get_timings(struct udevice * dev,struct display_timing * timings,u32 * bpp)322 static int mxs_of_get_timings(struct udevice *dev,
323 struct display_timing *timings,
324 u32 *bpp)
325 {
326 int ret = 0;
327 u32 display_phandle;
328 ofnode display_node;
329
330 ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
331 if (ret) {
332 dev_err(dev, "required display property isn't provided\n");
333 return -EINVAL;
334 }
335
336 display_node = ofnode_get_by_phandle(display_phandle);
337 if (!ofnode_valid(display_node)) {
338 dev_err(dev, "failed to find display subnode\n");
339 return -EINVAL;
340 }
341
342 ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
343 if (ret) {
344 dev_err(dev,
345 "required bits-per-pixel property isn't provided\n");
346 return -EINVAL;
347 }
348
349 ret = ofnode_decode_display_timing(display_node, 0, timings);
350 if (ret) {
351 dev_err(dev, "failed to get any display timings\n");
352 return -EINVAL;
353 }
354
355 return ret;
356 }
357
mxs_video_probe(struct udevice * dev)358 static int mxs_video_probe(struct udevice *dev)
359 {
360 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
361 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
362
363 struct display_timing timings;
364 u32 bpp = 0;
365 u32 fb_start, fb_end;
366 int ret;
367
368 debug("%s() plat: base 0x%lx, size 0x%x\n",
369 __func__, plat->base, plat->size);
370
371 ret = mxs_of_get_timings(dev, &timings, &bpp);
372 if (ret)
373 return ret;
374
375 ret = mxs_probe_common(dev, &timings, bpp, plat->base);
376 if (ret)
377 return ret;
378
379 switch (bpp) {
380 case 32:
381 case 24:
382 case 18:
383 uc_priv->bpix = VIDEO_BPP32;
384 break;
385 case 16:
386 uc_priv->bpix = VIDEO_BPP16;
387 break;
388 case 8:
389 uc_priv->bpix = VIDEO_BPP8;
390 break;
391 default:
392 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
393 return -EINVAL;
394 }
395
396 uc_priv->xsize = timings.hactive.typ;
397 uc_priv->ysize = timings.vactive.typ;
398
399 /* Enable dcache for the frame buffer */
400 fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
401 fb_end = plat->base + plat->size;
402 fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
403 mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
404 DCACHE_WRITEBACK);
405 video_set_flush_dcache(dev, true);
406 gd->fb_base = plat->base;
407
408 return ret;
409 }
410
mxs_video_bind(struct udevice * dev)411 static int mxs_video_bind(struct udevice *dev)
412 {
413 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
414 struct display_timing timings;
415 u32 bpp = 0;
416 u32 bytes_pp = 0;
417 int ret;
418
419 ret = mxs_of_get_timings(dev, &timings, &bpp);
420 if (ret)
421 return ret;
422
423 switch (bpp) {
424 case 32:
425 case 24:
426 case 18:
427 bytes_pp = 4;
428 break;
429 case 16:
430 bytes_pp = 2;
431 break;
432 case 8:
433 bytes_pp = 1;
434 break;
435 default:
436 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
437 return -EINVAL;
438 }
439
440 plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
441
442 return 0;
443 }
444
mxs_video_remove(struct udevice * dev)445 static int mxs_video_remove(struct udevice *dev)
446 {
447 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
448
449 mxs_remove_common(plat->base);
450
451 return 0;
452 }
453
454 static const struct udevice_id mxs_video_ids[] = {
455 { .compatible = "fsl,imx23-lcdif" },
456 { .compatible = "fsl,imx28-lcdif" },
457 { .compatible = "fsl,imx7ulp-lcdif" },
458 { .compatible = "fsl,imxrt-lcdif" },
459 { /* sentinel */ }
460 };
461
462 U_BOOT_DRIVER(mxs_video) = {
463 .name = "mxs_video",
464 .id = UCLASS_VIDEO,
465 .of_match = mxs_video_ids,
466 .bind = mxs_video_bind,
467 .probe = mxs_video_probe,
468 .remove = mxs_video_remove,
469 .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
470 };
471 #endif /* ifndef CONFIG_DM_VIDEO */
472