1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <display.h>
10 #include <dm.h>
11 #include <edid.h>
12 #include <log.h>
13 #include <regmap.h>
14 #include <syscon.h>
15 #include <video.h>
16 #include <asm/global_data.h>
17 #include <asm/gpio.h>
18 #include <asm/io.h>
19 #include <asm/arch-rockchip/clock.h>
20 #include <asm/arch-rockchip/edp_rk3288.h>
21 #include <asm/arch-rockchip/vop_rk3288.h>
22 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
24 #include <linux/bitops.h>
25 #include <linux/err.h>
26 #include <power/regulator.h>
27 #include "rk_vop.h"
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 enum vop_pol {
32 HSYNC_POSITIVE = 0,
33 VSYNC_POSITIVE = 1,
34 DEN_NEGATIVE = 2,
35 DCLK_INVERT = 3
36 };
37
rkvop_enable(struct rk3288_vop * regs,ulong fbbase,int fb_bits_per_pixel,const struct display_timing * edid)38 static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
39 int fb_bits_per_pixel,
40 const struct display_timing *edid)
41 {
42 u32 lb_mode;
43 u32 rgb_mode;
44 u32 hactive = edid->hactive.typ;
45 u32 vactive = edid->vactive.typ;
46
47 writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
48 ®s->win0_act_info);
49
50 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
51 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
52 ®s->win0_dsp_st);
53
54 writel(V_DSP_WIDTH(hactive - 1) |
55 V_DSP_HEIGHT(vactive - 1),
56 ®s->win0_dsp_info);
57
58 clrsetbits_le32(®s->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
59 V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
60
61 switch (fb_bits_per_pixel) {
62 case 16:
63 rgb_mode = RGB565;
64 writel(V_RGB565_VIRWIDTH(hactive), ®s->win0_vir);
65 break;
66 case 24:
67 rgb_mode = RGB888;
68 writel(V_RGB888_VIRWIDTH(hactive), ®s->win0_vir);
69 break;
70 case 32:
71 default:
72 rgb_mode = ARGB8888;
73 writel(V_ARGB888_VIRWIDTH(hactive), ®s->win0_vir);
74 break;
75 }
76
77 if (hactive > 2560)
78 lb_mode = LB_RGB_3840X2;
79 else if (hactive > 1920)
80 lb_mode = LB_RGB_2560X4;
81 else if (hactive > 1280)
82 lb_mode = LB_RGB_1920X5;
83 else
84 lb_mode = LB_RGB_1280X8;
85
86 clrsetbits_le32(®s->win0_ctrl0,
87 M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
88 V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
89 V_WIN0_EN(1));
90
91 writel(fbbase, ®s->win0_yrgb_mst);
92 writel(0x01, ®s->reg_cfg_done); /* enable reg config */
93 }
94
rkvop_set_pin_polarity(struct udevice * dev,enum vop_modes mode,u32 polarity)95 static void rkvop_set_pin_polarity(struct udevice *dev,
96 enum vop_modes mode, u32 polarity)
97 {
98 struct rkvop_driverdata *ops =
99 (struct rkvop_driverdata *)dev_get_driver_data(dev);
100
101 if (ops->set_pin_polarity)
102 ops->set_pin_polarity(dev, mode, polarity);
103 }
104
rkvop_enable_output(struct udevice * dev,enum vop_modes mode)105 static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
106 {
107 struct rk_vop_priv *priv = dev_get_priv(dev);
108 struct rk3288_vop *regs = priv->regs;
109
110 /* remove from standby */
111 clrbits_le32(®s->sys_ctrl, V_STANDBY_EN(1));
112
113 switch (mode) {
114 case VOP_MODE_HDMI:
115 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
116 V_HDMI_OUT_EN(1));
117 break;
118
119 case VOP_MODE_EDP:
120 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
121 V_EDP_OUT_EN(1));
122 break;
123
124 #if defined(CONFIG_ROCKCHIP_RK3288)
125 case VOP_MODE_LVDS:
126 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
127 V_RGB_OUT_EN(1));
128 break;
129 #endif
130
131 case VOP_MODE_MIPI:
132 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
133 V_MIPI_OUT_EN(1));
134 break;
135
136 default:
137 debug("%s: unsupported output mode %x\n", __func__, mode);
138 }
139 }
140
rkvop_mode_set(struct udevice * dev,const struct display_timing * edid,enum vop_modes mode)141 static void rkvop_mode_set(struct udevice *dev,
142 const struct display_timing *edid,
143 enum vop_modes mode)
144 {
145 struct rk_vop_priv *priv = dev_get_priv(dev);
146 struct rk3288_vop *regs = priv->regs;
147 struct rkvop_driverdata *data =
148 (struct rkvop_driverdata *)dev_get_driver_data(dev);
149
150 u32 hactive = edid->hactive.typ;
151 u32 vactive = edid->vactive.typ;
152 u32 hsync_len = edid->hsync_len.typ;
153 u32 hback_porch = edid->hback_porch.typ;
154 u32 vsync_len = edid->vsync_len.typ;
155 u32 vback_porch = edid->vback_porch.typ;
156 u32 hfront_porch = edid->hfront_porch.typ;
157 u32 vfront_porch = edid->vfront_porch.typ;
158 int mode_flags;
159 u32 pin_polarity;
160
161 pin_polarity = BIT(DCLK_INVERT);
162 if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
163 pin_polarity |= BIT(HSYNC_POSITIVE);
164 if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
165 pin_polarity |= BIT(VSYNC_POSITIVE);
166
167 rkvop_set_pin_polarity(dev, mode, pin_polarity);
168 rkvop_enable_output(dev, mode);
169
170 mode_flags = 0; /* RGB888 */
171 if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
172 (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP))
173 mode_flags = 15; /* RGBaaa */
174
175 clrsetbits_le32(®s->dsp_ctrl0, M_DSP_OUT_MODE,
176 V_DSP_OUT_MODE(mode_flags));
177
178 writel(V_HSYNC(hsync_len) |
179 V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
180 ®s->dsp_htotal_hs_end);
181
182 writel(V_HEAP(hsync_len + hback_porch + hactive) |
183 V_HASP(hsync_len + hback_porch),
184 ®s->dsp_hact_st_end);
185
186 writel(V_VSYNC(vsync_len) |
187 V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
188 ®s->dsp_vtotal_vs_end);
189
190 writel(V_VAEP(vsync_len + vback_porch + vactive)|
191 V_VASP(vsync_len + vback_porch),
192 ®s->dsp_vact_st_end);
193
194 writel(V_HEAP(hsync_len + hback_porch + hactive) |
195 V_HASP(hsync_len + hback_porch),
196 ®s->post_dsp_hact_info);
197
198 writel(V_VAEP(vsync_len + vback_porch + vactive)|
199 V_VASP(vsync_len + vback_porch),
200 ®s->post_dsp_vact_info);
201
202 writel(0x01, ®s->reg_cfg_done); /* enable reg config */
203 }
204
205 /**
206 * rk_display_init() - Try to enable the given display device
207 *
208 * This function performs many steps:
209 * - Finds the display device being referenced by @ep_node
210 * - Puts the VOP's ID into its uclass platform data
211 * - Probes the device to set it up
212 * - Reads the EDID timing information
213 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
214 * - Enables the display (the display device handles this and will do different
215 * things depending on the display type)
216 * - Tells the uclass about the display resolution so that the console will
217 * appear correctly
218 *
219 * @dev: VOP device that we want to connect to the display
220 * @fbbase: Frame buffer address
221 * @ep_node: Device tree node to process - this is the offset of an endpoint
222 * node within the VOP's 'port' list.
223 * @return 0 if OK, -ve if something went wrong
224 */
rk_display_init(struct udevice * dev,ulong fbbase,ofnode ep_node)225 static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
226 {
227 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
228 struct rk_vop_priv *priv = dev_get_priv(dev);
229 int vop_id, remote_vop_id;
230 struct rk3288_vop *regs = priv->regs;
231 struct display_timing timing;
232 struct udevice *disp;
233 int ret;
234 u32 remote_phandle;
235 struct display_plat *disp_uc_plat;
236 struct clk clk;
237 enum video_log2_bpp l2bpp;
238 ofnode remote;
239
240 debug("%s(%s, %lu, %s)\n", __func__,
241 dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
242
243 vop_id = ofnode_read_s32_default(ep_node, "reg", -1);
244 debug("vop_id=%d\n", vop_id);
245 ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
246 if (ret)
247 return ret;
248
249 remote = ofnode_get_by_phandle(remote_phandle);
250 if (!ofnode_valid(remote))
251 return -EINVAL;
252 remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
253 debug("remote vop_id=%d\n", remote_vop_id);
254
255 /*
256 * The remote-endpoint references into a subnode of the encoder
257 * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
258 * the following (assume 'hdmi_in_vopl' to be referenced):
259 *
260 * hdmi: hdmi@ff940000 {
261 * ports {
262 * hdmi_in: port {
263 * hdmi_in_vopb: endpoint@0 { ... };
264 * hdmi_in_vopl: endpoint@1 { ... };
265 * }
266 * }
267 * }
268 *
269 * The original code had 3 steps of "walking the parent", but
270 * a much better (as in: less likely to break if the DTS
271 * changes) way of doing this is to "find the enclosing device
272 * of UCLASS_DISPLAY".
273 */
274 while (ofnode_valid(remote)) {
275 remote = ofnode_get_parent(remote);
276 if (!ofnode_valid(remote)) {
277 debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
278 __func__, dev_read_name(dev));
279 return -EINVAL;
280 }
281
282 uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
283 if (disp)
284 break;
285 };
286
287 disp_uc_plat = dev_get_uclass_plat(disp);
288 debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
289 if (display_in_use(disp)) {
290 debug(" - device in use\n");
291 return -EBUSY;
292 }
293
294 disp_uc_plat->source_id = remote_vop_id;
295 disp_uc_plat->src_dev = dev;
296
297 ret = device_probe(disp);
298 if (ret) {
299 debug("%s: device '%s' display won't probe (ret=%d)\n",
300 __func__, dev->name, ret);
301 return ret;
302 }
303
304 ret = display_read_timing(disp, &timing);
305 if (ret) {
306 debug("%s: Failed to read timings\n", __func__);
307 return ret;
308 }
309
310 ret = clk_get_by_index(dev, 1, &clk);
311 if (!ret)
312 ret = clk_set_rate(&clk, timing.pixelclock.typ);
313 if (IS_ERR_VALUE(ret)) {
314 debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
315 return ret;
316 }
317
318 /* Set bitwidth for vop display according to vop mode */
319 switch (vop_id) {
320 case VOP_MODE_EDP:
321 #if defined(CONFIG_ROCKCHIP_RK3288)
322 case VOP_MODE_LVDS:
323 #endif
324 l2bpp = VIDEO_BPP16;
325 break;
326 case VOP_MODE_HDMI:
327 case VOP_MODE_MIPI:
328 l2bpp = VIDEO_BPP32;
329 break;
330 default:
331 l2bpp = VIDEO_BPP16;
332 }
333
334 rkvop_mode_set(dev, &timing, vop_id);
335 rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
336
337 ret = display_enable(disp, 1 << l2bpp, &timing);
338 if (ret)
339 return ret;
340
341 uc_priv->xsize = timing.hactive.typ;
342 uc_priv->ysize = timing.vactive.typ;
343 uc_priv->bpix = l2bpp;
344 debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
345
346 return 0;
347 }
348
rk_vop_probe_regulators(struct udevice * dev,const char * const * names,int cnt)349 void rk_vop_probe_regulators(struct udevice *dev,
350 const char * const *names, int cnt)
351 {
352 int i, ret;
353 const char *name;
354 struct udevice *reg;
355
356 for (i = 0; i < cnt; ++i) {
357 name = names[i];
358 debug("%s: probing regulator '%s'\n", dev->name, name);
359
360 ret = regulator_autoset_by_name(name, ®);
361 if (!ret)
362 ret = regulator_set_enable(reg, true);
363 }
364 }
365
rk_vop_probe(struct udevice * dev)366 int rk_vop_probe(struct udevice *dev)
367 {
368 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
369 struct rk_vop_priv *priv = dev_get_priv(dev);
370 int ret = 0;
371 ofnode port, node;
372
373 /* Before relocation we don't need to do anything */
374 if (!(gd->flags & GD_FLG_RELOC))
375 return 0;
376
377 priv->regs = (struct rk3288_vop *)dev_read_addr(dev);
378
379 /*
380 * Try all the ports until we find one that works. In practice this
381 * tries EDP first if available, then HDMI.
382 *
383 * Note that rockchip_vop_set_clk() always uses NPLL as the source
384 * clock so it is currently not possible to use more than one display
385 * device simultaneously.
386 */
387 port = dev_read_subnode(dev, "port");
388 if (!ofnode_valid(port)) {
389 debug("%s(%s): 'port' subnode not found\n",
390 __func__, dev_read_name(dev));
391 return -EINVAL;
392 }
393
394 for (node = ofnode_first_subnode(port);
395 ofnode_valid(node);
396 node = dev_read_next_subnode(node)) {
397 ret = rk_display_init(dev, plat->base, node);
398 if (ret)
399 debug("Device failed: ret=%d\n", ret);
400 if (!ret)
401 break;
402 }
403 video_set_flush_dcache(dev, 1);
404
405 return ret;
406 }
407
rk_vop_bind(struct udevice * dev)408 int rk_vop_bind(struct udevice *dev)
409 {
410 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
411
412 plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
413 CONFIG_VIDEO_ROCKCHIP_MAX_YRES);
414
415 return 0;
416 }
417