1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for one wire controller in some i.MX Socs
4 *
5 * There are currently two silicon variants:
6 * V1: i.MX21, i.MX27, i.MX31, i.MX51
7 * V2: i.MX25, i.MX35, i.MX50, i.MX53
8 * Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
9 *
10 * The V1 controller only supports single bit operations.
11 * The V2 controller is backwards compatible on the register level but adds
12 * byte size operations and a "search ROM accelerator mode"
13 *
14 * This driver does not currently support the search ROM accelerator
15 *
16 * Copyright (c) 2018 Flowbird
17 * Martin Fuzzey <martin.fuzzey@flowbird.group>
18 */
19
20 #include <common.h>
21 #include <asm/arch/clock.h>
22 #include <dm.h>
23 #include <dm/device_compat.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <linux/io.h>
27 #include <w1.h>
28
29 struct mxc_w1_regs {
30 u16 control;
31 #define MXC_W1_CONTROL_RPP BIT(7)
32 #define MXC_W1_CONTROL_PST BIT(6)
33 #define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
34 #define MXC_W1_CONTROL_RDST BIT(3)
35
36 u16 time_divider;
37 u16 reset;
38
39 /* Registers below on V2 silicon only */
40 u16 command;
41 u16 tx_rx;
42 u16 interrupt;
43 #define MXC_W1_INTERRUPT_TBE BIT(2)
44 #define MXC_W1_INTERRUPT_TSRE BIT(3)
45 #define MXC_W1_INTERRUPT_RBF BIT(4)
46 #define MXC_W1_INTERRUPT_RSRF BIT(5)
47
48 u16 interrupt_en;
49 };
50
51 struct mxc_w1_pdata {
52 struct mxc_w1_regs *regs;
53 };
54
55 /*
56 * this is the low level routine to read/write a bit on the One Wire
57 * interface on the hardware. It does write 0 if parameter bit is set
58 * to 0, otherwise a write 1/read.
59 */
mxc_w1_touch_bit(struct mxc_w1_pdata * pdata,u8 bit)60 static u8 mxc_w1_touch_bit(struct mxc_w1_pdata *pdata, u8 bit)
61 {
62 u16 *ctrl_addr = &pdata->regs->control;
63 u16 mask = MXC_W1_CONTROL_WR(bit);
64 unsigned int timeout_cnt = 400; /* Takes max. 120us according to
65 * datasheet.
66 */
67
68 writew(mask, ctrl_addr);
69
70 while (timeout_cnt--) {
71 if (!(readw(ctrl_addr) & mask))
72 break;
73
74 udelay(1);
75 }
76
77 return (readw(ctrl_addr) & MXC_W1_CONTROL_RDST) ? 1 : 0;
78 }
79
mxc_w1_read_byte(struct udevice * dev)80 static u8 mxc_w1_read_byte(struct udevice *dev)
81 {
82 struct mxc_w1_pdata *pdata = dev_get_plat(dev);
83 struct mxc_w1_regs *regs = pdata->regs;
84 u16 status;
85
86 if (dev_get_driver_data(dev) < 2) {
87 int i;
88 u8 ret = 0;
89
90 for (i = 0; i < 8; i++)
91 ret |= (mxc_w1_touch_bit(pdata, 1) << i);
92
93 return ret;
94 }
95
96 readw(®s->tx_rx);
97 writew(0xFF, ®s->tx_rx);
98
99 do {
100 udelay(1); /* Without this bytes are sometimes duplicated... */
101 status = readw(®s->interrupt);
102 } while (!(status & MXC_W1_INTERRUPT_RBF));
103
104 return (u8)readw(®s->tx_rx);
105 }
106
mxc_w1_write_byte(struct udevice * dev,u8 byte)107 static void mxc_w1_write_byte(struct udevice *dev, u8 byte)
108 {
109 struct mxc_w1_pdata *pdata = dev_get_plat(dev);
110 struct mxc_w1_regs *regs = pdata->regs;
111 u16 status;
112
113 if (dev_get_driver_data(dev) < 2) {
114 int i;
115
116 for (i = 0; i < 8; i++)
117 mxc_w1_touch_bit(pdata, (byte >> i) & 0x1);
118
119 return;
120 }
121
122 readw(®s->tx_rx);
123 writew(byte, ®s->tx_rx);
124
125 do {
126 udelay(1);
127 status = readw(®s->interrupt);
128 } while (!(status & MXC_W1_INTERRUPT_TSRE));
129 }
130
mxc_w1_reset(struct udevice * dev)131 static bool mxc_w1_reset(struct udevice *dev)
132 {
133 struct mxc_w1_pdata *pdata = dev_get_plat(dev);
134 u16 reg_val;
135
136 writew(MXC_W1_CONTROL_RPP, &pdata->regs->control);
137
138 do {
139 reg_val = readw(&pdata->regs->control);
140 } while (reg_val & MXC_W1_CONTROL_RPP);
141
142 return !(reg_val & MXC_W1_CONTROL_PST);
143 }
144
mxc_w1_triplet(struct udevice * dev,bool bdir)145 static u8 mxc_w1_triplet(struct udevice *dev, bool bdir)
146 {
147 struct mxc_w1_pdata *pdata = dev_get_plat(dev);
148 u8 id_bit = mxc_w1_touch_bit(pdata, 1);
149 u8 comp_bit = mxc_w1_touch_bit(pdata, 1);
150 u8 retval;
151
152 if (id_bit && comp_bit)
153 return 0x03; /* error */
154
155 if (!id_bit && !comp_bit) {
156 /* Both bits are valid, take the direction given */
157 retval = bdir ? 0x04 : 0;
158 } else {
159 /* Only one bit is valid, take that direction */
160 bdir = id_bit;
161 retval = id_bit ? 0x05 : 0x02;
162 }
163
164 mxc_w1_touch_bit(pdata, bdir);
165
166 return retval;
167 }
168
mxc_w1_of_to_plat(struct udevice * dev)169 static int mxc_w1_of_to_plat(struct udevice *dev)
170 {
171 struct mxc_w1_pdata *pdata = dev_get_plat(dev);
172 fdt_addr_t addr;
173
174 addr = dev_read_addr(dev);
175 if (addr == FDT_ADDR_T_NONE)
176 return -EINVAL;
177
178 pdata->regs = (struct mxc_w1_regs *)addr;
179
180 return 0;
181 };
182
mxc_w1_probe(struct udevice * dev)183 static int mxc_w1_probe(struct udevice *dev)
184 {
185 struct mxc_w1_pdata *pdata = dev_get_plat(dev);
186 unsigned int clkrate = mxc_get_clock(MXC_IPG_PERCLK);
187 unsigned int clkdiv;
188
189 if (clkrate < 10000000) {
190 dev_err(dev, "input clock frequency (%u Hz) too low\n",
191 clkrate);
192 return -EINVAL;
193 }
194
195 clkdiv = clkrate / 1000000;
196 clkrate /= clkdiv;
197 if (clkrate < 980000 || clkrate > 1020000) {
198 dev_err(dev, "Incorrect time base frequency %u Hz\n", clkrate);
199 return -EINVAL;
200 }
201
202 writew(clkdiv - 1, &pdata->regs->time_divider);
203
204 return 0;
205 }
206
207 static const struct w1_ops mxc_w1_ops = {
208 .read_byte = mxc_w1_read_byte,
209 .reset = mxc_w1_reset,
210 .triplet = mxc_w1_triplet,
211 .write_byte = mxc_w1_write_byte,
212 };
213
214 static const struct udevice_id mxc_w1_id[] = {
215 { .compatible = "fsl,imx21-owire", .data = 1 },
216 { .compatible = "fsl,imx27-owire", .data = 1 },
217 { .compatible = "fsl,imx31-owire", .data = 1 },
218 { .compatible = "fsl,imx51-owire", .data = 1 },
219
220 { .compatible = "fsl,imx25-owire", .data = 2 },
221 { .compatible = "fsl,imx35-owire", .data = 2 },
222 { .compatible = "fsl,imx50-owire", .data = 2 },
223 { .compatible = "fsl,imx53-owire", .data = 2 },
224 { },
225 };
226
227 U_BOOT_DRIVER(mxc_w1_drv) = {
228 .id = UCLASS_W1,
229 .name = "mxc_w1_drv",
230 .of_match = mxc_w1_id,
231 .of_to_plat = mxc_w1_of_to_plat,
232 .ops = &mxc_w1_ops,
233 .plat_auto = sizeof(struct mxc_w1_pdata),
234 .probe = mxc_w1_probe,
235 };
236