1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 */
5
6 #include <clk.h>
7 #include <common.h>
8 #include <dm.h>
9 #include <reset.h>
10 #include <wdt.h>
11 #include <asm/io.h>
12 #include <asm/utils.h>
13 #include <linux/bitops.h>
14
15 #define DW_WDT_CR 0x00
16 #define DW_WDT_TORR 0x04
17 #define DW_WDT_CRR 0x0C
18
19 #define DW_WDT_CR_EN_OFFSET 0x00
20 #define DW_WDT_CR_RMOD_OFFSET 0x01
21 #define DW_WDT_CRR_RESTART_VAL 0x76
22
23 struct designware_wdt_priv {
24 void __iomem *base;
25 unsigned int clk_khz;
26 };
27
28 /*
29 * Set the watchdog time interval.
30 * Counter is 32 bit.
31 */
designware_wdt_settimeout(void __iomem * base,unsigned int clk_khz,unsigned int timeout)32 static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
33 unsigned int timeout)
34 {
35 signed int i;
36
37 /* calculate the timeout range value */
38 i = log_2_n_round_up(timeout * clk_khz) - 16;
39 i = clamp(i, 0, 15);
40
41 writel(i | (i << 4), base + DW_WDT_TORR);
42
43 return 0;
44 }
45
designware_wdt_enable(void __iomem * base)46 static void designware_wdt_enable(void __iomem *base)
47 {
48 writel(BIT(DW_WDT_CR_EN_OFFSET), base + DW_WDT_CR);
49 }
50
designware_wdt_is_enabled(void __iomem * base)51 static unsigned int designware_wdt_is_enabled(void __iomem *base)
52 {
53 return readl(base + DW_WDT_CR) & BIT(0);
54 }
55
designware_wdt_reset_common(void __iomem * base)56 static void designware_wdt_reset_common(void __iomem *base)
57 {
58 if (designware_wdt_is_enabled(base))
59 /* restart the watchdog counter */
60 writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
61 }
62
63 #if !CONFIG_IS_ENABLED(WDT)
hw_watchdog_reset(void)64 void hw_watchdog_reset(void)
65 {
66 designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
67 }
68
hw_watchdog_init(void)69 void hw_watchdog_init(void)
70 {
71 /* reset to disable the watchdog */
72 hw_watchdog_reset();
73 /* set timer in miliseconds */
74 designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
75 CONFIG_DW_WDT_CLOCK_KHZ,
76 CONFIG_WATCHDOG_TIMEOUT_MSECS);
77 /* enable the watchdog */
78 designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
79 /* reset the watchdog */
80 hw_watchdog_reset();
81 }
82 #else
designware_wdt_reset(struct udevice * dev)83 static int designware_wdt_reset(struct udevice *dev)
84 {
85 struct designware_wdt_priv *priv = dev_get_priv(dev);
86
87 designware_wdt_reset_common(priv->base);
88
89 return 0;
90 }
91
designware_wdt_stop(struct udevice * dev)92 static int designware_wdt_stop(struct udevice *dev)
93 {
94 struct designware_wdt_priv *priv = dev_get_priv(dev);
95
96 designware_wdt_reset(dev);
97 writel(0, priv->base + DW_WDT_CR);
98
99 return 0;
100 }
101
designware_wdt_start(struct udevice * dev,u64 timeout,ulong flags)102 static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
103 {
104 struct designware_wdt_priv *priv = dev_get_priv(dev);
105
106 designware_wdt_stop(dev);
107
108 /* set timer in miliseconds */
109 designware_wdt_settimeout(priv->base, priv->clk_khz, timeout);
110
111 designware_wdt_enable(priv->base);
112
113 /* reset the watchdog */
114 return designware_wdt_reset(dev);
115 }
116
designware_wdt_probe(struct udevice * dev)117 static int designware_wdt_probe(struct udevice *dev)
118 {
119 struct designware_wdt_priv *priv = dev_get_priv(dev);
120 __maybe_unused int ret;
121
122 priv->base = dev_remap_addr(dev);
123 if (!priv->base)
124 return -EINVAL;
125
126 #if CONFIG_IS_ENABLED(CLK)
127 struct clk clk;
128
129 ret = clk_get_by_index(dev, 0, &clk);
130 if (ret)
131 return ret;
132
133 priv->clk_khz = clk_get_rate(&clk) / 1000;
134 if (!priv->clk_khz)
135 return -EINVAL;
136 #else
137 priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ;
138 #endif
139
140 #if CONFIG_IS_ENABLED(DM_RESET)
141 struct reset_ctl_bulk resets;
142
143 ret = reset_get_bulk(dev, &resets);
144 if (ret)
145 return ret;
146
147 ret = reset_deassert_bulk(&resets);
148 if (ret)
149 return ret;
150 #endif
151
152 /* reset to disable the watchdog */
153 return designware_wdt_stop(dev);
154 }
155
156 static const struct wdt_ops designware_wdt_ops = {
157 .start = designware_wdt_start,
158 .reset = designware_wdt_reset,
159 .stop = designware_wdt_stop,
160 };
161
162 static const struct udevice_id designware_wdt_ids[] = {
163 { .compatible = "snps,dw-wdt"},
164 {}
165 };
166
167 U_BOOT_DRIVER(designware_wdt) = {
168 .name = "designware_wdt",
169 .id = UCLASS_WDT,
170 .of_match = designware_wdt_ids,
171 .priv_auto = sizeof(struct designware_wdt_priv),
172 .probe = designware_wdt_probe,
173 .ops = &designware_wdt_ops,
174 .flags = DM_FLAG_PRE_RELOC,
175 };
176 #endif
177