1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * omap_wdt.c
4 *
5 * (C) Copyright 2013
6 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 *
8 * Based on:
9 *
10 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
11 *
12 * commit 2d991a164a61858012651e13c59521975504e260
13 * Author: Bill Pemberton <wfp5p@virginia.edu>
14 * Date: Mon Nov 19 13:21:41 2012 -0500
15 *
16 * watchdog: remove use of __devinit
17 *
18 * CONFIG_HOTPLUG is going away as an option so __devinit is no longer
19 * needed.
20 *
21 * Author: MontaVista Software, Inc.
22 * <gdavis@mvista.com> or <source@mvista.com>
23 *
24 * History:
25 *
26 * 20030527: George G. Davis <gdavis@mvista.com>
27 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
28 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
29 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
30 *
31 * Copyright (c) 2004 Texas Instruments.
32 * 1. Modified to support OMAP1610 32-KHz watchdog timer
33 * 2. Ported to 2.6 kernel
34 *
35 * Copyright (c) 2005 David Brownell
36 * Use the driver model and standard identifiers; handle bigger timeouts.
37 */
38
39 #include <common.h>
40 #include <log.h>
41 #include <watchdog.h>
42 #include <asm/arch/hardware.h>
43 #include <asm/io.h>
44 #include <asm/processor.h>
45 #include <asm/arch/cpu.h>
46 #include <wdt.h>
47 #include <dm.h>
48 #include <errno.h>
49
50 /* Hardware timeout in seconds */
51 #define WDT_HW_TIMEOUT 60
52
53 #if !CONFIG_IS_ENABLED(WDT)
54 static unsigned int wdt_trgr_pattern = 0x1234;
55
hw_watchdog_reset(void)56 void hw_watchdog_reset(void)
57 {
58 struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
59
60 /*
61 * Somebody just triggered watchdog reset and write to WTGR register
62 * is in progress. It is resetting right now, no need to trigger it
63 * again
64 */
65 if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
66 return;
67
68 wdt_trgr_pattern = ~wdt_trgr_pattern;
69 writel(wdt_trgr_pattern, &wdt->wdtwtgr);
70
71 /*
72 * Don't wait for posted write to complete, i.e. don't check
73 * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
74 * WTGR register outside of this func, and if entering it
75 * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
76 * was just triggered. This prevents us from wasting time in busy
77 * polling of WDT_WWPS_PEND_WTGR bit.
78 */
79 }
80
omap_wdt_set_timeout(unsigned int timeout)81 static int omap_wdt_set_timeout(unsigned int timeout)
82 {
83 struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
84 u32 pre_margin = GET_WLDR_VAL(timeout);
85
86 /* just count up at 32 KHz */
87 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
88 ;
89
90 writel(pre_margin, &wdt->wdtwldr);
91 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
92 ;
93
94 return 0;
95 }
96
hw_watchdog_disable(void)97 void hw_watchdog_disable(void)
98 {
99 struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
100
101 /*
102 * Disable watchdog
103 */
104 writel(0xAAAA, &wdt->wdtwspr);
105 while (readl(&wdt->wdtwwps) != 0x0)
106 ;
107 writel(0x5555, &wdt->wdtwspr);
108 while (readl(&wdt->wdtwwps) != 0x0)
109 ;
110 }
111
hw_watchdog_init(void)112 void hw_watchdog_init(void)
113 {
114 struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
115
116 /*
117 * Make sure the watchdog is disabled. This is unfortunately required
118 * because writing to various registers with the watchdog running has no
119 * effect.
120 */
121 hw_watchdog_disable();
122
123 /* initialize prescaler */
124 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
125 ;
126
127 writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &wdt->wdtwclr);
128 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
129 ;
130
131 omap_wdt_set_timeout(WDT_HW_TIMEOUT);
132
133 /* Sequence to enable the watchdog */
134 writel(0xBBBB, &wdt->wdtwspr);
135 while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
136 ;
137
138 writel(0x4444, &wdt->wdtwspr);
139 while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
140 ;
141 }
142
watchdog_reset(void)143 void watchdog_reset(void)
144 {
145 hw_watchdog_reset();
146 }
147
148 #else
149
omap3_wdt_reset(struct udevice * dev)150 static int omap3_wdt_reset(struct udevice *dev)
151 {
152 struct omap3_wdt_priv *priv = dev_get_priv(dev);
153
154 /*
155 * Somebody just triggered watchdog reset and write to WTGR register
156 * is in progress. It is resetting right now, no need to trigger it
157 * again
158 */
159 if ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
160 return 0;
161
162 priv->wdt_trgr_pattern = ~(priv->wdt_trgr_pattern);
163 writel(priv->wdt_trgr_pattern, &priv->regs->wdtwtgr);
164 /*
165 * Don't wait for posted write to complete, i.e. don't check
166 * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
167 * WTGR register outside of this func, and if entering it
168 * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
169 * was just triggered. This prevents us from wasting time in busy
170 * polling of WDT_WWPS_PEND_WTGR bit.
171 */
172 return 0;
173 }
174
omap3_wdt_stop(struct udevice * dev)175 static int omap3_wdt_stop(struct udevice *dev)
176 {
177 struct omap3_wdt_priv *priv = dev_get_priv(dev);
178
179 /* disable watchdog */
180 writel(0xAAAA, &priv->regs->wdtwspr);
181 while (readl(&priv->regs->wdtwwps) != 0x0)
182 ;
183 writel(0x5555, &priv->regs->wdtwspr);
184 while (readl(&priv->regs->wdtwwps) != 0x0)
185 ;
186 return 0;
187 }
188
omap3_wdt_start(struct udevice * dev,u64 timeout_ms,ulong flags)189 static int omap3_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
190 {
191 struct omap3_wdt_priv *priv = dev_get_priv(dev);
192 u32 pre_margin = GET_WLDR_VAL(timeout_ms / 1000);
193 /*
194 * Make sure the watchdog is disabled. This is unfortunately required
195 * because writing to various registers with the watchdog running has
196 * no effect.
197 */
198 omap3_wdt_stop(dev);
199
200 /* initialize prescaler */
201 while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
202 ;
203
204 writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &priv->regs->wdtwclr);
205 while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
206 ;
207 /* just count up at 32 KHz */
208 while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
209 ;
210
211 writel(pre_margin, &priv->regs->wdtwldr);
212 while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
213 ;
214 /* Sequence to enable the watchdog */
215 writel(0xBBBB, &priv->regs->wdtwspr);
216 while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
217 ;
218
219 writel(0x4444, &priv->regs->wdtwspr);
220 while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
221 ;
222
223 /* Trigger the watchdog to actually reload the counter. */
224 while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
225 ;
226
227 priv->wdt_trgr_pattern = ~(priv->wdt_trgr_pattern);
228 writel(priv->wdt_trgr_pattern, &priv->regs->wdtwtgr);
229
230 while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
231 ;
232
233 return 0;
234 }
235
omap3_wdt_probe(struct udevice * dev)236 static int omap3_wdt_probe(struct udevice *dev)
237 {
238 struct omap3_wdt_priv *priv = dev_get_priv(dev);
239
240 priv->regs = dev_read_addr_ptr(dev);
241 if (!priv->regs)
242 return -EINVAL;
243
244 priv->wdt_trgr_pattern = 0x1234;
245 debug("%s: Probing wdt%u\n", __func__, dev_seq(dev));
246 return 0;
247 }
248
249 static const struct wdt_ops omap3_wdt_ops = {
250 .start = omap3_wdt_start,
251 .stop = omap3_wdt_stop,
252 .reset = omap3_wdt_reset,
253 };
254
255 static const struct udevice_id omap3_wdt_ids[] = {
256 { .compatible = "ti,omap3-wdt" },
257 { }
258 };
259
260 U_BOOT_DRIVER(omap3_wdt) = {
261 .name = "omap3_wdt",
262 .id = UCLASS_WDT,
263 .of_match = omap3_wdt_ids,
264 .ops = &omap3_wdt_ops,
265 .probe = omap3_wdt_probe,
266 .priv_auto = sizeof(struct omap3_wdt_priv),
267 };
268 #endif /* !CONFIG_IS_ENABLED(WDT) */
269