1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <asm/io.h>
9 #include <asm/arch/imx-regs.h>
10
11 /*
12 * MX7ULP WDOG Register Map
13 */
14 struct wdog_regs {
15 u8 cs1;
16 u8 cs2;
17 u16 reserve0;
18 u32 cnt;
19 u32 toval;
20 u32 win;
21 };
22
23 #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
24 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
25 #endif
26
27 #define REFRESH_WORD0 0xA602 /* 1st refresh word */
28 #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
29
30 #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
31 #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
32
33 #define WDGCS1_WDGE (1<<7)
34 #define WDGCS1_WDGUPDATE (1<<5)
35
36 #define WDGCS2_FLG (1<<6)
37
38 #define WDG_BUS_CLK (0x0)
39 #define WDG_LPO_CLK (0x1)
40 #define WDG_32KHZ_CLK (0x2)
41 #define WDG_EXT_CLK (0x3)
42
hw_watchdog_set_timeout(u16 val)43 void hw_watchdog_set_timeout(u16 val)
44 {
45 /* setting timeout value */
46 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
47
48 writel(val, &wdog->toval);
49 }
50
hw_watchdog_reset(void)51 void hw_watchdog_reset(void)
52 {
53 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
54
55 writel(REFRESH_WORD0, &wdog->cnt);
56 writel(REFRESH_WORD1, &wdog->cnt);
57 }
58
hw_watchdog_init(void)59 void hw_watchdog_init(void)
60 {
61 u8 val;
62 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
63
64 writel(UNLOCK_WORD0, &wdog->cnt);
65 writel(UNLOCK_WORD1, &wdog->cnt);
66
67 val = readb(&wdog->cs2);
68 val |= WDGCS2_FLG;
69 writeb(val, &wdog->cs2);
70
71 hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
72 writel(0, &wdog->win);
73
74 writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
75 writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */
76
77 hw_watchdog_reset();
78 }
79
reset_cpu(ulong addr)80 void reset_cpu(ulong addr)
81 {
82 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
83
84 writel(UNLOCK_WORD0, &wdog->cnt);
85 writel(UNLOCK_WORD1, &wdog->cnt);
86
87 hw_watchdog_set_timeout(5); /* 5ms timeout */
88 writel(0, &wdog->win);
89
90 writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
91 writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */
92
93 hw_watchdog_reset();
94
95 while (1);
96 }
97